Texas Instruments XIO2213B Evaluation Module / Reference Design XIO2213BEVM XIO2213BEVM 데이터 시트
제품 코드
XIO2213BEVM
SCPS210F – OCTOBER 2008 – REVISED MAY 2013
4.27 Capabilities Pointer Register
This read-only register provides a pointer into the PCI configuration header where the PCI power
management block resides. Since the PCI power-management registers begin at 50h, this register is
hardwired to 50h.
management block resides. Since the PCI power-management registers begin at 50h, this register is
hardwired to 50h.
PCI register offset:
34h
Register type:
Read only
Default value:
50h
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
0
1
0
1
0
0
0
0
4.28 Interrupt Line Register
This read/write register is programmed by the system and indicates to the software which interrupt line the
bridge has assigned to it. The default value of this register is FFh, indicating that an interrupt line has not
yet been assigned to the function. Since the bridge does not generate interrupts internally, this register is
a scratchpad register.
bridge has assigned to it. The default value of this register is FFh, indicating that an interrupt line has not
yet been assigned to the function. Since the bridge does not generate interrupts internally, this register is
a scratchpad register.
PCI register offset:
3Ch
Register type:
Read/Write
Default value:
FFh
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
1
1
1
1
1
1
1
1
4.29 Interrupt Pin Register
The interrupt pin register is read-only 00h indicating that the bridge does not generate internal interrupts.
While the bridge does not generate internal interrupts, it does forward interrupts from the secondary
interface to the primary interface.
While the bridge does not generate internal interrupts, it does forward interrupts from the secondary
interface to the primary interface.
PCI register offset:
3Dh
Register type:
Read only
Default value:
00h
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
0
0
62
Classic PCI Configuration Space
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