Texas Instruments XIO2213B Evaluation Module / Reference Design XIO2213BEVM XIO2213BEVM 데이터 시트
제품 코드
XIO2213BEVM
SCPS210F – OCTOBER 2008 – REVISED MAY 2013
4.30
Bridge Control Register
The bridge control register provides extensions to the command register that are specific to a bridge. See
for a complete description of the register contents.
PCI register offset:
3Eh
Register type:
Read only, Read/Write, Read/Clear
Default value:
0000h
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-18. Bridge Control Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
15:12
RSVD
R
Reserved. Returns 0h when read.
11
DTSERR
RW
Discard timer SERR enable. Applies only in conventional PCI mode. This bit enables the
bridge to generate either an ERR_NONFATAL (by default) or ERR_FATAL transaction on
the primary interface when the secondary discard timer expires and a delayed transaction
is discarded from a queue in the bridge. The severity is selectable only if advanced error
reporting is supported.
bridge to generate either an ERR_NONFATAL (by default) or ERR_FATAL transaction on
the primary interface when the secondary discard timer expires and a delayed transaction
is discarded from a queue in the bridge. The severity is selectable only if advanced error
reporting is supported.
0 = Do not generate ERR_NONFATAL or ERR_FATAL on the primary interface as a
result of the expiration of the secondary discard timer. Note that an error message
can still be sent if advanced error reporting is supported and bit 10
(DISCARD_TIMER_MASK) in the secondary uncorrectable error mask register
(offset 130h, see
can still be sent if advanced error reporting is supported and bit 10
(DISCARD_TIMER_MASK) in the secondary uncorrectable error mask register
(offset 130h, see
) is clear (default).
1 = Generate ERR_NONFATAL or ERR_FATAL on the primary interface if the
secondary discard timer expires and a delayed transaction is discarded from a
queue in the bridges.
queue in the bridges.
10
DTSTATUS
RCU
Discard timer status. This bit indicates if a discard timer expires and a delayed transaction
is discarded.
is discarded.
0 = No discard timer error
1 = Discard timer error
9
SEC_DT
RW selects the number of PCI clocks that the bridge waits for the 1394a OHCI master on
the secondary interface to repeat a delayed transaction request. The counter starts once
the delayed completion (the completion of the delayed transaction on the primary
interface) has reached the head of the downstream queue of the bridge (i.e., all ordering
requirements have been satisfied and the bridge is ready to complete the delayed
transaction with the initiating master on the secondary bus). If the master does not repeat
the transaction before the counter expires, the bridge deletes the delayed transaction from
its queue and sets the discard timer status bit.
the secondary interface to repeat a delayed transaction request. The counter starts once
the delayed completion (the completion of the delayed transaction on the primary
interface) has reached the head of the downstream queue of the bridge (i.e., all ordering
requirements have been satisfied and the bridge is ready to complete the delayed
transaction with the initiating master on the secondary bus). If the master does not repeat
the transaction before the counter expires, the bridge deletes the delayed transaction from
its queue and sets the discard timer status bit.
0 = Secondary discard timer counts 2
15
PCI clock cycles (default).
1 = Secondary discard timer counts 2
10
PCI clock cycles.
8
PRI_DEC
R
Primary discard timer. This bit has no meaning in PCIe and is hardwired to 0b.
7
FBB_EN
RW
Fast back-to-back enable. This bit allows software to enable fast back-to-back
transactions on the secondary PCI interface.
transactions on the secondary PCI interface.
0 = Fast back-to-back transactions are disabled (default).
1 = Secondary interface fast back-to-back transactions are enabled.
6
SRST
RW
Secondary bus reset. This bit is set when software wishes to reset all devices
downstream of the bridge. Setting this bit causes the PRST signal on the secondary
interface to be asserted.
downstream of the bridge. Setting this bit causes the PRST signal on the secondary
interface to be asserted.
0 = Secondary interface is not in reset state (default).
1 = Secondary interface is in the reset state.
Copyright © 2008–2013, Texas Instruments Incorporated
Classic PCI Configuration Space
63
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