Microchip Technology MA240029 데이터 시트
2010-2011 Microchip Technology Inc.
DS39996F-page 245
PIC24FJ128GA310 FAMILY
bit 4
RXINV:
Receive Polarity Inversion bit
1
= UxRX Idle state is ‘0’
0
= UxRX Idle state is ‘1’
bit 3
BRGH:
High Baud Rate Enable bit
1
= High-Speed mode (4 BRG clock cycles per bit)
0
= Standard Speed mode (16 BRG clock cycles per bit)
bit 2-1
PDSEL<1:0>:
Parity and Data Selection bits
11
= 9-bit data, no parity
10
= 8-bit data, odd parity
01
= 8-bit data, even parity
00
= 8-bit data, no parity
bit 0
STSEL:
Stop Bit Selection bit
1
= Two Stop bits
0
= One Stop bit
REGISTER 18-1:
UxMODE: UARTx MODE REGISTER (CONTINUED)
Note 1:
If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. See
Section 11.4 “Peripheral Pin Select (PPS)”
for more information.
2:
This feature is only available for the 16x BRG mode (BRGH = 0).