Freescale Semiconductor FRDM-FXS-MULTI 데이터 시트
FXOS8700CQ
Sensors
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
37
10.1.4
TRIG_CFG (0x0A) register
FIFO trigger configuration register. After the interrupt flag of the enabled event in TRIG_CFG is set, the FIFO (when configured
in Trigger mode) is gated at the time of the interrupt event preventing the further collection of data samples. This allows the host
processor to analyze the data leading up to the event detection (up to 32 samples). For detailed information on how to utilize the
FIFO and the various trigger events, please see AN4073 available on the Freescale website.
in Trigger mode) is gated at the time of the interrupt event preventing the further collection of data samples. This allows the host
processor to analyze the data leading up to the event detection (up to 32 samples). For detailed information on how to utilize the
FIFO and the various trigger events, please see AN4073 available on the Freescale website.
10.1.5
SYSMOD (0x0B) register
The system mode register indicates the current device operating mode. Applications using the Auto-Sleep/Auto-Wake
mechanism should use this register to synchronize their application with the device operating mode. The system mode register
also indicates the status of the FIFO gate error flag and the time elapsed since the FIFO gate error flag was asserted.
mechanism should use this register to synchronize their application with the device operating mode. The system mode register
also indicates the status of the FIFO gate error flag and the time elapsed since the FIFO gate error flag was asserted.
Table 23. TRIG_CFG register
—
—
trig_trans
trig_lndprt
trig_pulse
trig_ffmt
trig_a_vecm
—
0
0
0
0
0
0
0
0
Table 24. TRIG_CFG bit descriptions
Field
Description
trig_trans
Transient interrupt FIFO trigger enable.
trig_lndprt
Landscape/Portrait orientation interrupt FIFO trigger enable.
trig_pulse
Pulse interrupt FIFO trigger enable
trig_ffmt
Freefall/motion interrupt FIFO trigger enable
trig_a_vecm
Acceleration vector-magnitude FIFO trigger enable.
Table 25. SYSMOD register
fgerr
fgt[4:0]
sysmod[1:0]
0b0
0b0_0000
0b00
Table 26. SYSMOD bit description
Field
Description
fgerr
FIFO gate error. Default value: 0.
0: No FIFO gate error detected.
1: FIFO gate error was detected.
Emptying the FIFO buffer clears the fgerr bit in the SYSMOD register.
See CTRL_REG3 [Interrupt CTRL register] (0x2C) for more information on configuring the FIFO Gate function.
0: No FIFO gate error detected.
1: FIFO gate error was detected.
Emptying the FIFO buffer clears the fgerr bit in the SYSMOD register.
See CTRL_REG3 [Interrupt CTRL register] (0x2C) for more information on configuring the FIFO Gate function.
fgt[4:0]
Number of ODR time units since fgerr was asserted. Reset when fgerr is cleared
sysmod[1:0]
System mode. Default value: 0b00.
0b00: Standby mode
0b01: Wake mode
0b01: Sleep mode
0b00: Standby mode
0b01: Wake mode
0b01: Sleep mode