Freescale Semiconductor FRDM-FXS-MULTI 데이터 시트
FXOS8700CQ
Sensors
46
Freescale Semiconductor, Inc.
10.2
Auto-Sleep trigger
10.2.1
ASLP_COUNT (0x29) register
The ASLP_COUNT register sets the minimum time period of event flag inactivity required to initiate a change from the current
active mode ODR value specified in CTRL_REG1[dr] to the Sleep mode ODR value specified in CTRL_REG1[aslp_rate],
provided that CTRL_REG2[slpe] = 1.
active mode ODR value specified in CTRL_REG1[dr] to the Sleep mode ODR value specified in CTRL_REG1[aslp_rate],
provided that CTRL_REG2[slpe] = 1.
See
for functional blocks that may be monitored for inactivity in order to trigger the return-to-sleep event.
Please note that when the device is operated in hybrid mode, the effective ODR is half of what is selected in CTRL_REG1[dr].
For example, with ODR = 800 Hz and the device set to hybrid mode, the ASLP_COUNT time step becomes 640 ms.
For example, with ODR = 800 Hz and the device set to hybrid mode, the ASLP_COUNT time step becomes 640 ms.
*
If the fifo_gate bit is set to logic ‘1’, the assertion of the SRC_ASLP interrupt does not prevent the system from transitioning to Sleep or from Wake mode; instead
it prevents the FIFO buffer from accepting new sample data until the host application flushes the FIFO buffer.
it prevents the FIFO buffer from accepting new sample data until the host application flushes the FIFO buffer.
The interrupt sources listed in
affect the auto-sleep, return to sleep and wake from sleep mechanism only if they have
been previously enabled. The functional block event flags that are bypassed while the system is in Auto-Sleep mode are
temporary disabled (see
temporary disabled (see
for more
information) and are automatically re-enabled when the device returns from Auto-Sleep mode (that is, wakes up), except for the
data ready function.
data ready function.
Table 44. ASLP_COUNT register
aslp_cnt[7:0]
0b0000_0000
Table 45. ASLP_COUNT bit description
Field
Description
aslp_cnt[7:0]
See
for details
Table 46. ASLP_COUNT relationship with ODR
Output Data Rate (ODR)
Maximum inactivity time (s)
ODR time step (ms)
ASLP_COUNT step (ms)
800
81
1.25
320
400
81
2.5
320
200
81
5
320
100
81
10
320
50
81
20
320
12.5
81
80
320
6.25
81
160
320
1.56
63
640
640
Table 47. Sleep/Wake mode gates and triggers
Interrupt source
Event restarts time and
delays Return-to-Sleep
Event will Wake-from-Sleep
SRC_FIFO
Yes
No
SRC_TRANS
Yes
Yes
SRC_LNDPRT
Yes
Yes
SRC_PULSE
Yes
Yes
SRC_FFMT
Yes
Yes
SRC_ASLP
No*
No*
SRC_Mag
Yes
Yes
SRC_DRDY
No
No
SRC_AVECM
Yes
Yes
SRC_MVECM
Yes
Yes
SRC_MTHS
Yes
Yes