Texas Instruments TMS320C642x DSP 사용자 설명서
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2.5
Memory Width and Byte Alignment
DDR2 memory controller data bus
DDR_D[31:24]
DDR_D[23:16]
DDR_D[15:8]
DDR_D[7:0]
32-bit memory device
16-bit memory device
Peripheral Architecture
The DDR2 memory controller supports memory widths of 16 bits and 32 bits.
summarizes the
addressable memory ranges on the DDR2 memory controller. See the device-specific data manual for the
memory widths that are supported. Both big-endian and little-endian formats are supported.
memory widths that are supported. Both big-endian and little-endian formats are supported.
shows the byte lanes used on the DDR2 memory controller. The external memory is always
right-aligned on the data bus.
Table 5. Addressable Memory Ranges
Memory Width
Maximum addressable bytes per CS space
Description
×
16
128 Mbytes
Halfword address
×
32
256 Mbytes
Word address
Figure 11. Byte Alignment (Little-Endian Mode)
DDR2 Memory Controller
20
SPRUEM4A – November 2007