Texas Instruments TMS320C642x DSP 사용자 설명서
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2.6
Endianness Support
Peripheral Architecture
The DDR2 memory controller supports both big-endian and little-endian operating modes. The endianness
mode selection at the time of an access determines the order in which data on the internal data bus is
written to or read from devices that are not as wide as the internal data bus. However, the DDR2 memory
controller maintains the natural order of endian operations. That is, a stream of data starting at any
address N within any endian environment will always be accessed in the correct or incrementing data
order. The DDR2 memory controller will always access address N prior to N + 1 in all endian modes and
in any data width.
mode selection at the time of an access determines the order in which data on the internal data bus is
written to or read from devices that are not as wide as the internal data bus. However, the DDR2 memory
controller maintains the natural order of endian operations. That is, a stream of data starting at any
address N within any endian environment will always be accessed in the correct or incrementing data
order. The DDR2 memory controller will always access address N prior to N + 1 in all endian modes and
in any data width.
and
show operation of the DDR2 memory controller for both 16-bit and
32-bit external memory in both big-endian and little-endian modes. See the device-specific data manual
for the memory widths that are supported.
for the memory widths that are supported.
Since the endianness mode must be determined prior to bootloading, the endian mode selection is latched
in the Boot Configuration (BOOTCFG) register when the device is reset. This endianness mode selection
is also reflected in the BE bit in the SDRAM status register (SDRSTAT).
in the Boot Configuration (BOOTCFG) register when the device is reset. This endianness mode selection
is also reflected in the BE bit in the SDRAM status register (SDRSTAT).
Table 6. 16-Bit External Memory
Big-Endian Mode
Little-Endian Mode
Internal Data (64-Bit)
DDR_A[2:1]
DDR_D[15:0]
DDR_A[2:1]
DDR_D[15:0]
0123 4567 89AB CDEFh
00
0123h
00
CDEFh
0123 4567 89AB CDEFh
01
4567h
01
89ABh
0123 4567 89AB CDEFh
10
89ABh
10
4567h
0123 4567 89AB CDEFh
11
CDEFh
11
0123h
Table 7. 32-Bit External Memory
Big-Endian Mode
Little-Endian Mode
Internal Data (64-Bit)
DDR_A[2]
DDR_D[31:0]
DDR_A[2]
DDR_D[31:0]
0123 4567 89AB CDEFh
0
89AB CDEFh
0
89AB CDEFh
0123 4567 89AB CDEFh
1
0123 4567h
1
0123 4567h
SPRUEM4A – November 2007
DDR2 Memory Controller
21