Intel P4500 사용자 매뉴얼

차례

• Features Summary

  9
• Introduction

  9
• Platform

  10
• Processor Feature Details

  11
• 1.2.1 Supported Technologies

  11
• Interfaces

  11
• 1.3.1 System Memory Support

  11
• 1.3.2 PCI Express*

  12
• 1.3.3 Direct Media Interface (DMI)

  13
• 1.3.4 Platform Environment Control Interface (PECI)

  14
• 1.3.5 Intel® HD Graphics Controller

  14
• 1.3.6 Embedded DisplayPort* (eDP*)

  15
• 1.3.7 Intel® Flexible Display Interface (Intel® FDI)

  15
• Power Management Support

  15
• 1.4.1 Processor Core

  15
• 1.4.2 System

  15
• 1.4.3 Memory Controller

  16
• 1.4.4 PCI Express*

  16
• 1.4.5 DMI

  16
• 1.4.6 Integrated Graphics Controller

  16
• Thermal Management Support

  16
• Package

  16
• Terminology

  17
• Related Documents

  19
• Interfaces

  20
• System Memory Interface

  20
• 2.1.1 System Memory Technology Supported

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• 2-1 Supported SO-DIMM Module Configurations1

  20
• 2.1.2 System Memory Timing Support

  21
• 2.1.3 System Memory Organization Modes

  21
• 2-2 DDR3 System Memory Timing Support

  21
• 2-2 Intel Flex Memory Technology Operation

  22
• 2.1.4 Rules for Populating Memory Slots

  23
• 2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)

  24
• 2.1.6 DRAM Clock Generation

  24
• 2.1.7 System Memory Pre-Charge Power Down Support Details

  24
• PCI Express Interface

  25
• 2.2.1 PCI Express Architecture

  25
• 2-4 PCI Express Layering Diagram

  25
• 2-5 Packet Flow through the Layers

  26
• 2.2.2 PCI Express Configuration Mechanism

  27
• 2.2.3 PCI Express Ports and Bifurcation

  27
• 2-6 PCI Express Related Register Structures in the Processor

  27
• DMI

  28
• 2.3.1 DMI Error Flow

  28
• 2.3.2 Processor/PCH Compatibility Assumptions

  28
• 2.3.3 DMI Link Down

  28
• Intel® HD Graphics Controller

  29
• 2.4.1 3D and Video Engines for Graphics Processing

  29
• 2-7 Integrated Graphics Controller Unit Block Diagram

  29
• 2.4.2 Integrated Graphics Display Pipes

  32
• 2-8 Processor Display Block Diagram

  32
• 2-3 eDP/PEG Ball Mapping

  33
• 2.4.3 Intel Flexible Display Interface

  34
• Platform Environment Control Interface (PECI)

  34
• Interface Clocking

  35
• 2.6.1 Internal Clocking Requirements

  35
• 2-4 Processor Reference Clocks

  35
• Technologies

  36
• Intel® Virtualization Technology

  36
• 3.1.1 Intel® VT-x Objectives

  36
• 3.1.2 Intel® VT-x Features

  36
• Intel Graphics Dynamic Frequency

  37
• ACPI States Supported

  38
• 4.1.1 System States

  38
• 4.1.2 Processor Core/Package Idle States

  38
• 4-5 System States

  38
• 4-6 Processor Core/Package State Support

  38
• 4.1.3 Integrated Memory Controller States

  39
• 4.1.4 PCIe Link States

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• 4.1.5 DMI States

  39
• 4.1.6 Integrated Graphics Controller States

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• 4-7 Integrated Memory Controller States

  39
• 4-8 PCIe Link States

  39
• 4-9 DMI States

  39
• 4-10 Integrated Graphics Controller States

  39
• 4.1.7 Interface State Combinations

  40
• Processor Core Power Management

  40
• 4-11 G, S and C State Combinations

  40
• 4-12 D, S, and C State Combination

  40
• 4.2.1 Enhanced Intel SpeedStep® Technology

  41
• 4.2.2 Low-Power Idle States

  41
• 4-9 Idle Power Management Breakdown of the Processor Cores

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• 4-10 Thread and Core C-State Entry and Exit

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• 4.2.3 Requesting Low-Power Idle States

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• 4-13 Coordination of Thread Power States at the Core Level

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• 4-14 P_LVLx to MWAIT Conversion

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• 4.2.4 Core C-states

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• 4.2.5 Package C-States

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• 4-15 Coordination of Core Power States at the Package Level

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• 4-11 Package C-State Entry and Exit

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• IMC Power Management

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• 4.3.1 Disabling Unused System Memory Outputs

  49
• 4.3.2 DRAM Power Management and Initialization

  49
• PCIe Power Management

  50
• 4-16 Targeted Memory State Conditions

  50
• DMI Power Management

  51
• Integrated Graphics Power Management

  51
• 4.6.1 Intel® Display Power Saving Technology 5.0 (Intel ® DPST 5.0)

  51
• 4.6.2 Graphics Render C-State

  51
• 4.6.3 Graphics Performance Modulation Technology

  51
• 4.6.4 Intel® Smart 2D Display Technology (Intel® S2DDT)

  51
• Thermal Power Management

  52
• Thermal Design Power and Junction Temperature

  53
• 5.1.1 Intel Graphics Dynamic Frequency

  53
• Specifications

  54
• 5.1.3 Idle Power Specifications

  56
• Specifications

  56
• 5-18 18 W Ultra Low Voltage (ULV) Processor Idle Power

  56
• 5.1.4 Intelligent Power Sharing Control Overview

  57
• 5-19 35 W Standard Voltage (SV) Processor Idle Power

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• 5.1.5 Component Power Measurement/Estimation Error

  58
• Thermal Management Features

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• 5.2.1 Processor Core Thermal Features

  58
• 5-12 Frequency and Voltage Ordering

  60
• 5.2.2 Integrated Graphics and Memory Controller Thermal Features

  65
• 5.2.3 Platform Environment Control Interface (PECI)

  68
• 6-20 Signal Description Buffer Types

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• System Memory Interface

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• 6-21 Memory Channel A

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• 6-22 Memory Channel B

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• Memory Reference and Compensation

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• 6-23 Memory Reference and Compensation

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• Reset and Miscellaneous Signals

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• 6-24 Reset and Miscellaneous Signals

  74
• PCI Express Graphics Interface Signals

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• 6-25 PCI Express Graphics Interface Signals

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• Embedded DisplayPort (eDP)

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• Intel Flexible Display Interface Signals

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• 6-26 Intel® Flexible Display Interface

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• DMI

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• PLL Signals

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• 6-27 DMI - Processor to PCH Serial Interface

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• 6-28 PLL Signals

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• TAP Signals

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• 6-29 TAP Signals

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• Error and Thermal Protection

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• 6-30 Error and Thermal Protection

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• Power Sequencing

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• 6-31 Power Sequencing

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• Processor Power Signals

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• 6-32 Processor Power Signals

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• Ground and NCTF

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• Processor Internal Pull Up/Pull Down

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• 6-33 Ground and NCTF

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• 6-34 Processor Internal Pull Up/Pull Down

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• Electrical Specifications

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• Power and Ground Pins

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• Decoupling Guidelines

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• 7.2.1 Voltage Rail Decoupling

  85
• Processor Clocking (BCLK, BCLK#)

  85
• 7.3.1 PLL Power Supply

  86
• Voltage Identification (VID)

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• 7-35 Voltage Identification Definition

  86
• Reserved or Unused Signals

  90
• 7-36 Market Segment Selection Truth Table for MSID[2:0]

  90
• Signal Groups

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• 7-37 Signal Groups1

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• Test Access Port (TAP) Connection

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• Absolute Maximum and Minimum Ratings

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• Storage Conditions Specifications

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• 7-38 Processor Absolute Minimum and Maximum Ratings

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• DC Specifications

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• 7-39 Storage Condition Ratings

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• 7.10.1 Voltage and Current Specifications

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• 7-13 Active VCC and ICC Loadline (PSI# Asserted)

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• 7-14 Active VCC and ICC Loadline (PSI# Not Asserted)

  97
• Processor Uncore I/O Buffer Supply DC Voltage and Current Specifications

  98
• 7-15 VAXG/IAXG Static and Ripple Voltage Regulation

  99
• Specifications

  99
• DDR3 Signal Group DC Specifications

  100
• Control Sideband and TAP Signal Group DC Specifications

  101
• PCI Express DC Specifications

  102
• Platform Environmental Control Interface (PECI) DC Specifications

  103
• 7.11.1 DC Characteristics

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• eDP DC Specifications

  103
• 7.11.2 Input Device Hysteresis

  104
• 7-16 Input Device Hysteresis

  104
• PECI DC Electrical Limits

  104
• Processor Pin and Signal Information

  105
• Processor Pin Assignments

  105
• 8-17 Socket-G (rPGA988A) Pinmap (Top View, Upper-Left Quadrant)

  106
• 8-18 Socket-G (rPGA988A) Pinmap (Top View, Upper-Right Quadrant)

  107
• 8-19 Socket-G (rPGA988A) Pinmap (Top View, Lower-Left Quadrant)

  108
• 8-20 Socket-G (rPGA988A) Pinmap (Top View, Lower-Right Quadrant)

  109
• rPGA988A Processor Pin List by Pin Number

  110
• rPGA988A Processor Pin List by Pin Name

  124
• 8-21 BGA1288 Ballmap (Top View, Upper-Left Quadrant)

  138
• 8-22 BGA1288 Ballmap (Top View, Upper-Right Quadrant)

  139
• 8-23 BGA1288 Ballmap (Top View, Lower-Left Quadrant)

  140
• 8-24 BGA1288 Ballmap (Top View, Lower-Right Quadrant)

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• BGA1288 Processor Ball List by Ball Name

  142
• BGA1288 Processor Ball List by Ball Number

  160
• Package Mechanical Information

  179
• 8-25 rPGA Mechanical Package (Sheet 1 of 2)

  179
• 8-26 rPGA Mechanical Package (Sheet 2 of 2)

  180
• 8-27 BGA Mechanical Package (Sheet 2 of 2)

  181