데이터 시트 (EU80574XL088N)차례Intel® Core™2 Extreme Processor QX97751Contents3Figures4Tables4Revision History5Intel® Core™2 Extreme Processor QX9775 Features71 Introduction91.1 Terminology101.2 References122 Electrical Specifications132.1 Front Side Bus and GTLREF132.2 Power and Ground Lands132.3 Decoupling Guidelines142.3.1 VCC Decoupling142.3.2 VTT Decoupling142.3.3 Front Side Bus AGTL+ Decoupling142.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking15Table 2-1. Core Frequency to FSB Multiplier Configuration152.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])16Table 2-2. BSEL[2:0] Frequency Table162.4.2 PLL Power Supply162.5 Voltage Identification (VID)17Table 2-3. Voltage Identification Definition18Table 2-4. Loadline Selection Truth Table for LL_ID[1:0]19Table 2-5. Market Segment Selection Truth Table for MS_ID[1:0]192.6 Reserved, Unused, and Test Signals192.7 Front Side Bus Signal Groups20Table 2-6. FSB Signal Groups (Sheet 1 of 2)20Table 2-7. AGTL+ Signal Description Table21Table 2-8. Non AGTL+ Signal Description Table21Table 2-9. Signal Reference Voltages222.8 CMOS Asynchronous and Open Drain Asynchronous Signals222.9 Test Access Port (TAP) Connection222.10 Platform Environmental Control Interface (PECI) DC Specifications222.10.1 DC Characteristics22Table 2-10. PECI DC Electrical Limits232.10.2 Input Device Hysteresis23Figure 2-1. Input Device Hysteresis232.11 Mixing Processors242.12 Absolute Maximum and Minimum Ratings24Table 2-11. Processor Absolute Maximum Ratings252.13 Processor DC Specifications25Table 2-12. Voltage and Current Specifications26Figure 2-2. Processor Load Current versus Time27Table 2-13. Processor VCC Static and Transient Tolerance28Figure 2-3. Processor VCC Static and Transient Tolerance Load Lines29Table 2-14. AGTL+ Signal Group DC Specifications29Table 2-15. CMOS Signal Input/Output Group and TAP Signal Group DC Specifications30Table 2-16. Open Drain Output Signal Group DC Specifications302.13.1 VCC Overshoot Specification30Table 2-17. VCC Overshoot Specifications30Figure 2-4. VCC Overshoot Example Waveform312.13.2 Die Voltage Validation312.14 AGTL+ FSB Specifications32Table 2-18. AGTL+ Bus Voltage Definitions32Table 2-19. FSB Differential BCLK Specifications33Figure 2-5. Differential Clock Waveform34Figure 2-6. Differential Clock Crosspoint Specification34Figure 2-7. Differential Rising and Falling Edge Rates343 Mechanical Specifications35Figure 3-1. Processor Package Assembly Sketch353.1 Package Mechanical Drawings35Figure 3-2. Processor Package Drawing (Sheet 1 of 3)36Figure 3-3. Processor Package Drawing (Sheet 2 of 3)37Figure 3-4. Processor Package Drawing (Sheet 3 of 3)383.2 Processor Component Keepout Zones393.3 Package Loading Specifications39Table 3-1. Package Loading Specifications393.4 Package Handling Guidelines40Table 3-2. Package Handling Guidelines403.5 Package Insertion Specifications403.6 Processor Mass Specifications403.7 Processor Materials40Table 3-3. Processor Materials403.8 Processor Markings41Figure 3-5. Processor Top-side Markings (Example)413.9 Processor Land Coordinates42Figure 3-6. Processor Land Coordinates, Top View42Figure 3-7. Processor Land Coordinates, Bottom View434 Land Listing and Signal Description454.1 Land Listing45Table 4-1. Land Listing by Land Name (Sheet 1 of 17)46Table 4-2. Land Listing by Land Number (Sheet 1 of 17)554.2 Signal Definitions64Table 4-1. Signal Definitions (Sheet 1 of 11)645 Thermal Specifications755.1 Package Thermal Specifications755.1.1 Thermal Specifications75Table 5-1. Processor Thermal Specifications76Figure 5-1. Processor Thermal Profile76Table 5-2. Processor Thermal Profile Table775.1.2 Thermal Metrology77Figure 5-2. Case Temperature (TCASE) Measurement Location785.2 Processor Thermal Features785.2.1 Intel® Thermal Monitor Features785.2.1.1 Thermal Monitor (TM1)785.2.1.2 Enhanced Thermal Monitor (TM2)79Figure 5-3. Thermal Monitor 2 Frequency and Voltage Ordering805.2.2 On-Demand Mode805.2.3 PROCHOT# Signal805.2.4 FORCEPR# Signal815.2.5 THERMTRIP# Signal815.3 Platform Environment Control Interface (PECI)815.3.1 Introduction81Figure 5-4. Processor PECI Topology825.3.1.1 TCONTROL and TCC Activation on PECI-based Systems83Figure 5-5. Conceptual Fan Control Diagram of PECI-based Platforms835.3.1.2 Processor Thermal Data Sample Rate and Filtering835.3.2 PECI Specifications845.3.2.1 PECI Device Address845.3.2.2 PECI Command Support845.3.2.3 PECI Fault Handling Requirements845.3.2.4 PECI GetTemp0()and GetTemp1() Error Code Support84Table 5-3. GetTemp0() GetTemp1()Error Codes846 Features856.1 Power-On Configuration Options85Table 6-1. Power-On Configuration Option Lands856.2 Clock Control and Low Power States85Figure 6-1. Stop Clock State Machine866.2.1 Normal State866.2.2 HALT or Extended HALT State866.2.2.1 HALT State866.2.2.2 Extended HALT State87Table 6-2. Extended HALT Maximum Power876.2.3 Stop-Grant State876.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State886.2.4.1 HALT Snoop State, Stop Grant Snoop State886.2.4.2 Extended HALT Snoop State886.3 Enhanced Intel SpeedStep® Technology89크기: 960킬로바이트페이지: 90Language: English매뉴얼 열기