Manuali utente per Intel QX9775

Sommario

• Intel® Core™2 Extreme Processor QX9775

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  • Contents

    3
    • Figures

      4
    • Tables

      4
  • Revision History

    5
  • Intel® Core™2 Extreme Processor QX9775 Features

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• 1 Introduction

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  • 1.1 Terminology

    10
  • 1.2 References

    12
• 2 Electrical Specifications

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  • 2.1 Front Side Bus and GTLREF

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  • 2.2 Power and Ground Lands

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  • 2.3 Decoupling Guidelines

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    • 2.3.1 VCC Decoupling

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    • 2.3.2 VTT Decoupling

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    • 2.3.3 Front Side Bus AGTL+ Decoupling

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  • 2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

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    • Table 2-1. Core Frequency to FSB Multiplier Configuration

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    • 2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])

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      • Table 2-2. BSEL[2:0] Frequency Table

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    • 2.4.2 PLL Power Supply

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  • 2.5 Voltage Identification (VID)

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    • Table 2-3. Voltage Identification Definition

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    • Table 2-4. Loadline Selection Truth Table for LL_ID[1:0]

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    • Table 2-5. Market Segment Selection Truth Table for MS_ID[1:0]

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  • 2.6 Reserved, Unused, and Test Signals

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  • 2.7 Front Side Bus Signal Groups

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    • Table 2-6. FSB Signal Groups (Sheet 1 of 2)

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    • Table 2-7. AGTL+ Signal Description Table

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    • Table 2-8. Non AGTL+ Signal Description Table

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    • Table 2-9. Signal Reference Voltages

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  • 2.8 CMOS Asynchronous and Open Drain Asynchronous Signals

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  • 2.9 Test Access Port (TAP) Connection

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  • 2.10 Platform Environmental Control Interface (PECI) DC Specifications

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    • 2.10.1 DC Characteristics

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      • Table 2-10. PECI DC Electrical Limits

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    • 2.10.2 Input Device Hysteresis

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      • Figure 2-1. Input Device Hysteresis

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  • 2.11 Mixing Processors

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  • 2.12 Absolute Maximum and Minimum Ratings

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    • Table 2-11. Processor Absolute Maximum Ratings

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  • 2.13 Processor DC Specifications

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    • Table 2-12. Voltage and Current Specifications

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    • Figure 2-2. Processor Load Current versus Time

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    • Table 2-13. Processor VCC Static and Transient Tolerance

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    • Figure 2-3. Processor VCC Static and Transient Tolerance Load Lines

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    • Table 2-14. AGTL+ Signal Group DC Specifications

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    • Table 2-15. CMOS Signal Input/Output Group and TAP Signal Group DC Specifications

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    • Table 2-16. Open Drain Output Signal Group DC Specifications

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    • 2.13.1 VCC Overshoot Specification

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      • Table 2-17. VCC Overshoot Specifications

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      • Figure 2-4. VCC Overshoot Example Waveform

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    • 2.13.2 Die Voltage Validation

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  • 2.14 AGTL+ FSB Specifications

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    • Table 2-18. AGTL+ Bus Voltage Definitions

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    • Table 2-19. FSB Differential BCLK Specifications

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    • Figure 2-5. Differential Clock Waveform

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    • Figure 2-6. Differential Clock Crosspoint Specification

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    • Figure 2-7. Differential Rising and Falling Edge Rates

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• 3 Mechanical Specifications

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  • Figure 3-1. Processor Package Assembly Sketch

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  • 3.1 Package Mechanical Drawings

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    • Figure 3-2. Processor Package Drawing (Sheet 1 of 3)

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    • Figure 3-3. Processor Package Drawing (Sheet 2 of 3)

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    • Figure 3-4. Processor Package Drawing (Sheet 3 of 3)

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  • 3.2 Processor Component Keepout Zones

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  • 3.3 Package Loading Specifications

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    • Table 3-1. Package Loading Specifications

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  • 3.4 Package Handling Guidelines

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    • Table 3-2. Package Handling Guidelines

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  • 3.5 Package Insertion Specifications

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  • 3.6 Processor Mass Specifications

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  • 3.7 Processor Materials

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    • Table 3-3. Processor Materials

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  • 3.8 Processor Markings

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    • Figure 3-5. Processor Top-side Markings (Example)

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  • 3.9 Processor Land Coordinates

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    • Figure 3-6. Processor Land Coordinates, Top View

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    • Figure 3-7. Processor Land Coordinates, Bottom View

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• 4 Land Listing and Signal Description

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  • 4.1 Land Listing

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    • Table 4-1. Land Listing by Land Name (Sheet 1 of 17)

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    • Table 4-2. Land Listing by Land Number (Sheet 1 of 17)

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  • 4.2 Signal Definitions

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    • Table 4-1. Signal Definitions (Sheet 1 of 11)

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• 5 Thermal Specifications

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  • 5.1 Package Thermal Specifications

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    • 5.1.1 Thermal Specifications

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      • Table 5-1. Processor Thermal Specifications

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      • Figure 5-1. Processor Thermal Profile

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      • Table 5-2. Processor Thermal Profile Table

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    • 5.1.2 Thermal Metrology

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      • Figure 5-2. Case Temperature (TCASE) Measurement Location

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  • 5.2 Processor Thermal Features

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    • 5.2.1 Intel® Thermal Monitor Features

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      • 5.2.1.1 Thermal Monitor (TM1)

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      • 5.2.1.2 Enhanced Thermal Monitor (TM2)

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        • Figure 5-3. Thermal Monitor 2 Frequency and Voltage Ordering

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    • 5.2.2 On-Demand Mode

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    • 5.2.3 PROCHOT# Signal

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    • 5.2.4 FORCEPR# Signal

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    • 5.2.5 THERMTRIP# Signal

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  • 5.3 Platform Environment Control Interface (PECI)

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    • 5.3.1 Introduction

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      • Figure 5-4. Processor PECI Topology

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      • 5.3.1.1 TCONTROL and TCC Activation on PECI-based Systems

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        • Figure 5-5. Conceptual Fan Control Diagram of PECI-based Platforms

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      • 5.3.1.2 Processor Thermal Data Sample Rate and Filtering

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    • 5.3.2 PECI Specifications

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      • 5.3.2.1 PECI Device Address

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      • 5.3.2.2 PECI Command Support

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      • 5.3.2.3 PECI Fault Handling Requirements

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      • 5.3.2.4 PECI GetTemp0()and GetTemp1() Error Code Support

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        • Table 5-3. GetTemp0() GetTemp1()Error Codes

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• 6 Features

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  • 6.1 Power-On Configuration Options

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    • Table 6-1. Power-On Configuration Option Lands

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  • 6.2 Clock Control and Low Power States

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    • Figure 6-1. Stop Clock State Machine

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    • 6.2.1 Normal State

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    • 6.2.2 HALT or Extended HALT State

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      • 6.2.2.1 HALT State

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      • 6.2.2.2 Extended HALT State

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        • Table 6-2. Extended HALT Maximum Power

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    • 6.2.3 Stop-Grant State

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    • 6.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State

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      • 6.2.4.1 HALT Snoop State, Stop Grant Snoop State

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      • 6.2.4.2 Extended HALT Snoop State

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  • 6.3 Enhanced Intel SpeedStep® Technology

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