Texas Instruments 2-A Peak Sink/Source DDR Termination Regulator With VTTREF Buffered Reference TPS51206EVM-745 TPS51206EVM-745 데이터 시트
제품 코드
TPS51206EVM-745
EVM Assembly Drawing and PCB Layout
7.7
DDR3 (0.75VTT) Bode Plot
Test condition: 5 Vin, VLDOIN = VDDQ = 1.5 V, VTT = VTTREF = 0.75 V, I
VTT
= 2 A Source Current
Phase Margin: 58.7Deg, Gain Margin: 7.6dB, Crossover Frequency: 1MHz
Figure 24. DDR3 Bode plot
8
EVM Assembly Drawing and PCB Layout
through
show the design of the TPS51206EVM-745 printed-circuit board. The EVM
has been designed using a four-layer, 2-oz copper, printed-circuit board.
21
SLUU515
–
August 2011
Using the TPS51206EVM-745, 2-A Peak Sink/Source DDR Termination
Regulator With VTTREF Buffered Reference for DDR2, DDR3, DDR3L, and
Copyright
©
2011, Texas Instruments Incorporated
DDR4