Fujitsu SPARC64 V Manual Do Utilizador
Release 1.0, 1 July 2002
F. Chapter P
Error Handling
187
58
16
30
16
DMMU_TAG_ACCESS
RW
Parity
LDXA
#D
IUG_TSBP
W (WotherD)
58
16
38
16
DMMU_VA_WATCHPOINT
RW
Parity
Enabled
LDXA
(I)AUG_CRE
I(A)UG_CRE
I(A)UG_CRE
W
W
W
58
16
40
16
DMMU_PA_WATCHPOINT
RW
Parity
Enabled
LDXA
(I)AUG_CRE
I(A)UG_CRE
I(A)UG_CRE
W
W
W
58
16
48
16
DMMU_TSB_PEXT
RW
Parity
=
DTSB_BASE
I(A)UG_TSBCTXT
W
58
16
50
16
DMMU_TSB_SEXT
RW
Parity
=
DTSB_BASE
I(A)UG_TSBCTXT
W
58
16
58
16
DMMU_TSB_NEXT
R
Parity
=
DTSB_BASE
I(A)UG_TSBCTXT
None
59
16
—
DMMU_TSB_8KB_PTR
R
PP
LDXA
IUG_TSBP
WotherD
5A
16
—
DMMU_TSB_64KB_PTR
R
PP
LDXA
IUG_TSBP
WotherD
5B
16
—
DMMU_TSB_DIRECT_PTR
R
PP
LDXA
IUG_TSBP
WotherD
5C
16
—
DTLB_DATA_IN
W
Parity
DTLB
write
IUG_DTLB
DemapAll
5D
16
—
DTLB_DATA_ACCESS
RW
Parity
LDXA
DTLB
write
IUG_DTLB
IUG_DTLB
IUG_DTLB
DemapAll
DemapAll
DemapAll
5E
16
—
DTLB_TAG_READ
R
Parity
LDXA
IUG_DTLB
DemapAll
5F
16
—
DMMU_DEMAP
W
Parity
DTLB
write
IUG_DTLB
DemapAll
60
16
—
IIU_INST_TRAP
RW
Parity
LDXA
No match at error
W
6E
16
00
16
EIDR
RW
Parity
Always
IAUG_CRE
W
6F
16
—
parallel barrier assist
RW
Parity
AUG
always
LDXA
BV interface
Not detected (#dv)
COREERROR
(#dv)
(I)AUG_CRE
W
W
None
W
None
77
16
40
16
–
88
16
INTR_DATA0:7_W
INTR_DISPATCH_W
W
W
W
Gecc
Gecc
Gecc
None
store
store
—
(I)AUG_CRE
W
W
W
7F
16
40
16
–
88
16
INTR_DATA0:7_R
R
ECC
LDXA
intr_receive
COREERROR
(#dv)
BUSY
= 0
Interrupt
Receive
Receive
EF
16
—
Parallel barrier assist
RW
Parity
AUG
always
LDXA
BV interface
Not detected (#dv)
COREERROR
(#dv)
(I)AUG_CRE
W
W
None
W
None
TABLE P-20
Handling of ASI Register Errors (Continued)
ASI
VA
Register Name
RW
Error
Protect
Protect
Error Detect
Condition
Condition
Error Type
Correction