Fujitsu SPARC64 V Manual Do Utilizador
Release 1.0, 1 July 2002
F. Chapter P
Error Handling
189
When a parity error is detected in a D1 cache tag entry or in a D1 cache tag copy
entry, hardware automatically corrects the error by copying the correct tag entry
from the other copy of the tag entry. If the error can be corrected in this way,
program execution is unaffected.
entry, hardware automatically corrects the error by copying the correct tag entry
from the other copy of the tag entry. If the error can be corrected in this way,
program execution is unaffected.
Similarly, when a parity error is detected in an I1 cache tag entry or in a I1 cache tag
copy entry, hardware automatically corrects the error by copying the correct tag
entry from the other copy of the tag entry. If the error can be corrected in this way,
program execution is unaffected.
copy entry, hardware automatically corrects the error by copying the correct tag
entry from the other copy of the tag entry. If the error can be corrected in this way,
program execution is unaffected.
When the error in the level-1 cache tag or tag copy is not corrected by the tag
copying operation, the tag copying is repeated. If the error is permanent, a watchdog
timeout or a FATAL error is then detected.
copying operation, the tag copying is repeated. If the error is permanent, a watchdog
timeout or a FATAL error is then detected.
Error in U2 (Unified Level 2) Cache Tag
The U2 cache tag is protected by double-bit error detection and single-bit error
correction ECC code.
correction ECC code.
When a correctable error is detected in a U2 cache tag, hardware automatically
corrects the error by rewriting the corrected data into the U2 cache tag entry. The
error is not reported to software.
corrects the error by rewriting the corrected data into the U2 cache tag entry. The
error is not reported to software.
When an uncorrectable error is detected in a U2 cache tag, one of following actions
is taken, depending on the setting of
is taken, depending on the setting of
OPSR
(internal mode register set by the JTAG
command):
1. A fatal error is detected and the CPU enters the CPU fatal error state.
2. The U2 cache tag uncorrectable error is treated as follows; however, in some cases,
the fatal error is still detected.
a. When
ASI_ERROR_CONTROL.WEAK_ED
= 0:
The
AUG_SDC
is recognized during U2 cache tag error detection.
If
ASI_ERROR_CONTROL.UGE_HANDLER
= 0, the
AUG_SDC
immediately
generates an
async_data_error
trap with
ASI_UGESR.AUG_SDC
= 1.
Otherwise:, if
ASI_ERROR_CONTROL.UGE_HANDLER
= 1, the
AUG_SDC
remains
pending in hardware. At the point when
ASI_ERROR_CONTROL.UGE_HANDLER
is set to 0, an
async_data_error
exception
is generated, with
ASI_UGESR.AUG_SDC
= 1.
b. When
ASI_ERROR_CONTROL.WEAK_ED
= 1:
Hardware ignores the U2 cache tag error if possible. However, the
AUG_SDC
or
fatal error may still be detected.