Kenwood TK-2102G Manual Do Utilizador
TK-2102G
7
CIRCUIT DESCRIPTION
XF200:L71-0522-05
Item
Rating
Nominal center frequency
38.850MHz
Pass band width
±5.0kHz or more at 3dB
40dB stop band width
±20.0kHz or less
Ripple
1.0dB or less
Insertion loss
4.0dB or less
Guaranteed attenuation
80dB or more at fo -910kHz
Terminal impedance
610Ω /3PF
CF200:L72-0958-05
Item
Rating
Nominal center frequency
450kHz
6dB band width
±6.0kHz or more
50dB band width
±12.5kHz or less
Ripple
2.0dB or less at fo ±4kHz
Insertion loss
6.0dB or less
Guaranteed attenuation
35.0dB or more at fo ±100kHz
Terminal impedance
2.0 kΩ
5) Squelch
Part of the AF signal from the IC enters the FM IC again,
and the noise component is amplifi ed and rectifi ed by a fi lter
and an amplifi er to produce a DC voltage corresponding to
the noise level.
and an amplifi er to produce a DC voltage corresponding to
the noise level.
The DC signal from the FM IC goes to the analog port of
6) Receive Signaling
QT/DQT
300 Hz and higher audio frequencies of the output signal
300 Hz and higher audio frequencies of the output signal
from IF IC are cut by a low-pass fi lter (IC301). The resulting
signal enters the microprocessor (IC403). IC403 determines
whether the QT or DQT matches the preset value, and con-
trols the MUTE and AFCO and the speaker output sounds
according to the squelch results.
signal enters the microprocessor (IC403). IC403 determines
whether the QT or DQT matches the preset value, and con-
trols the MUTE and AFCO and the speaker output sounds
according to the squelch results.
3. PLL Frequency Synthesizer
The PLL circuit generates the fi rst local oscillator signal
for reception and the RF signal for transmission.
1) PLL
The frequency step of the PLL circuit is 5 or 6.25kHz.
A 12.8MHz reference oscillator signal is divided at IC1 by
A 12.8MHz reference oscillator signal is divided at IC1 by
a fi xed counter to produce the 5 or 6.25kHz reference fre-
quency. The voltage controlled oscillator (VCO) output signal
is buffer amplifi ed by Q6, then divided in IC1 by a dual-mod-
ule programmable counter . The divided signal is compared
in phase with the 5 or 6.25kHz reference signal in the phase
comparator in IC1. The output signal from the phase com-
parator is fi ltered through a low-pass fi lter and passed to the
VCO to control the oscillator frequency. (See Fig.4)
quency. The voltage controlled oscillator (VCO) output signal
is buffer amplifi ed by Q6, then divided in IC1 by a dual-mod-
ule programmable counter . The divided signal is compared
in phase with the 5 or 6.25kHz reference signal in the phase
comparator in IC1. The output signal from the phase com-
parator is fi ltered through a low-pass fi lter and passed to the
VCO to control the oscillator frequency. (See Fig.4)
the microprocessor (IC403). IC403 determines whether to
output sounds from the speaker by checking whether the
input voltage is higher or lower than the preset value.
output sounds from the speaker by checking whether the
input voltage is higher or lower than the preset value.
To output sounds from the speaker, IC403 sends a high
signal to the MUTE and AFCO Iines and turns IC302 on
through Q302, Q304, Q305, Q306 and Q307.(See Fig. 3)
through Q302, Q304, Q305, Q306 and Q307.(See Fig. 3)
Fig. 3 AF amplifi er and squelch
FM IF IC
IC200
IF AMP
DET
DET
HPF
AMP
AMP
LPF
IC301
QT/DQT
Q303
W/N SW
W/N SW
IC403
MPU
BUSY
MUTE
AFCO
TI
6
5
67
62
AF AMP
IC300
LPF
HPF
Q302
SW
IC302
AF PA AMP
Q307
SW
SW
SP
Q304, 305, 306