Freescale Semiconductor Evaluation Kit (EVK) for the i.MX51 Applications Processor MCIMX51LCD MCIMX51LCD Ficha De Dados
Códigos do produto
MCIMX51LCD
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 6
72
Freescale Semiconductor
Electrical Characteristics
NOTE
Measurements are taken from Vref to Vref (cross-point to cross-point), but
JEDEC timings for single-ended signals are defined from Vref to Vil(ac)
max or to Vih(ac) min.
JEDEC timings for single-ended signals are defined from Vref to Vil(ac)
max or to Vih(ac) min.
Table 61. Derating values for DDR2 Differential DQS
1
,
2
Table 62. Derating values for DDR2 Single Ended DQS
3
,
4
1. Test conditions are: Capacitance 15 pF for DDR PADS. Recommended drive strengths is medium for SDCLK and high for
address and controls.
2. SDRAM CLK and DQS related parameters are being measured from the 50% point. that is, high is defined as 50% of signal
value and low is defined as 50% as signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK
and SDCLK (inverted clock).
and SDCLK (inverted clock).
3. Test conditions are: Capacitance 15 pF for DDR PADS. Recommended drive strengths is medium for SDCLK and high for
address and controls.
4. SDRAM CLK and DQS related parameters are being measured from the 50% point. that is, high is defined as 50% of signal
value and low is defined as 50% as signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK
and SDCLK (inverted clock).
and SDCLK (inverted clock).