Freescale Semiconductor Evaluation Kit (EVK) for the i.MX51 Applications Processor MCIMX51LCD MCIMX51LCD Ficha De Dados
Códigos do produto
MCIMX51LCD
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 6
74
Freescale Semiconductor
Electrical Characteristics
4.7
External Peripheral Interfaces
The following sections provide information on external peripheral interfaces.
4.7.1
CSPI Timing Parameters
This section describes the timing parameters of the CSPI. The CSPI has separate timing parameters for
master and slave modes. The nomenclature used with the CSPI modules and the respective routing of
these signals is shown in
master and slave modes. The nomenclature used with the CSPI modules and the respective routing of
these signals is shown in
4.7.1.1
CSPI Master Mode Timing
depicts the timing of CSPI in Master mode and
lists the CSPI Master Mode timing
characteristics.
Figure 38. CSPI Master Mode Timing Diagram
Table 64. CSPI Nomenclature and Routing
Module
I/O Access
eCSPI1
CSPI1
1
, USBH1, and DI1 via IOMUX
1
This set of BGA contacts is labeled CSPI, but is actually an eCSPI channel
eCSPI2
NANDF and USBH1 via IOMUX
CSPI
NANDF, USBH1, SD1, SD2, and GPIO via IOMUX
Table 65. CSPI Master Mode Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
CS1
SCLK Cycle Time
t
clk
60
—
ns
CS2
SCLK High or Low Time
t
SW
26
—
ns
CS3
SCLK Rise or Fall
1
t
RISE/FALL
—
—
ns
CS4
SSx pulse width
t
CSLH
26
—
ns
CS1
CS7
CS2
CS2
CS4
CS6
CS5
CS8
CS9
SCLK
SSx
MOSI
MISO
RDY
CS10
CS3
CS3