Freescale Semiconductor Evaluation Kit (EVK) for the i.MX51 Applications Processor MCIMX51LCD MCIMX51LCD Ficha De Dados
Códigos do produto
MCIMX51LCD
Electrical Characteristics
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 6
Freescale Semiconductor
73
shows the timing diagram for DDR2 SDRM read cycle. The timing parameters for this diagram
appear in
.
Figure 37. DDR2 SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram
NOTE
It is recommended to perform read calibration process in order to achieve
the best performance.
the best performance.
Table 63. DDR2 SDRAM Read Cycle Parameter Table
ID
Parameter
Symbol
SDCLK = 200 MHz
Unit
Min
Max
DDR24
1
1
The actual timing may vary depending on read calibration settings. What is actually important for the controller is
DDR25-DDR24 which results in the minimum required DQ valid window width: 1.8ns-0.5ns = 1.3ns of minimum width.
DDR25-DDR24 which results in the minimum required DQ valid window width: 1.8ns-0.5ns = 1.3ns of minimum width.
DQS—DQ Skew (defines the Data valid window during read cycles
related to DQS).
related to DQS).
t
DQSQ
—
0.5
ns
DDR25
2
2
The actual timing may vary depending on read calibration settings. What is actually important for the controller is
DDR25-DDR24 which results in the minimum required DQ valid window width: 1.8ns-0.5ns = 1.3ns of minimum width.
DDR25-DDR24 which results in the minimum required DQ valid window width: 1.8ns-0.5ns = 1.3ns of minimum width.
DQ HOLD time from DQS
t
QH
1.8
—
ns
SDCLK
SDCLK_B
DQS (input)
DQ (input)
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DDR25
DDR24