Freescale Semiconductor Tower System Module S12G240 TWR-S12G240 TWR-S12G240 Ficha De Dados
Códigos do produto
TWR-S12G240
Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual,
Rev.1.23
214
Freescale Semiconductor
NOTE
If the input is driven to active level (IRQ=0) a write access to set either
IRQCR[IRQEN] and IRQCR[IRQE] to 1 simultaneously or to set
IRQCR[IRQEN] to 1 when IRQCR[IRQE]=1 causes an IRQ interrupt to be
generated if the I-bit is cleared. Refer to
IRQCR[IRQEN] and IRQCR[IRQE] to 1 simultaneously or to set
IRQCR[IRQEN] to 1 when IRQCR[IRQE]=1 causes an IRQ interrupt to be
generated if the I-bit is cleared. Refer to
2.4.3.14
Reserved Register
1
Read: Anytime
Write:
Write:
IRQE: Once in normal mode, anytime in special mode
IRQEN: Anytime
IRQEN: Anytime
Table 2-34. IRQCR Register Field Descriptions
Field
Description
7
IRQE
IRQ select edge sensitive only—
1 IRQ pin configured to respond only to falling edges. Falling edges on the IRQ pin are detected anytime when
IRQE=1 and will be cleared only upon a reset or the servicing of the IRQ interrupt.
0 IRQ pin configured for low level recognition
6
IRQEN
IRQ enable—
1 IRQ pin is connected to interrupt logic
0 IRQ pin is disconnected from interrupt logic
0 IRQ pin is disconnected from interrupt logic
Address 0x001F
Access: User read/write
1
1
Read: Anytime
Write: Only in special mode
Write: Only in special mode
These reserved registers are designed for factory test purposes only and are
not intended for general user access. Writing to these registers when in
special mode can alter the module’s functionality.
not intended for general user access. Writing to these registers when in
special mode can alter the module’s functionality.
7
6
5
4
3
2
1
0
R
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
W
Reset
x
x
x
x
x
x
x
x
Figure 2-15. Reserved Register