Freescale Semiconductor Reference Design System for MPC8308 MPC8308-RDB MPC8308-RDB Manual Do Utilizador
Códigos do produto
MPC8308-RDB
PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-62
Freescale Semiconductor
14.4.6
PCI Express Controller Internal Control and Status Registers (CSRs)
This section describes the PCI Express controller internal control and status registers.
14.4.6.1
PCI Express LTSSM State Status Register (PEX_LTSSM_STAT)
PEX_LTSSM_STAT, shown in
, provides details on link training status. This register is useful
for debugging link training failures.
The fields of the PEX_LTSSM_STAT
provides the encodings for the status code field of the PEX_LTSSM_STAT register.
Offset 0x404
Access: Read-only
31
7
6
0
R
—
Status Code
W
Reset
All zeros
Figure 14-77. PCI Express LTSSM State Status Register (PEX_LTSSM_STAT)
Table 14-74. PEX_LTSSM_STAT Fields Description
Bits
Name
Description
31–7
—
Reserved
6–0
Status code
Status code. See
for encodings.
Table 14-75. PEX_LTSSM_STAT Status Codes
Status Code
(Hex)
LTSSM State Description
Status Code
(Hex)
LTSSM State Description
00
Detect quiet
27
TX L0s FTS; RX L0s FTS
01
Detect active (0)
28
L0 to L1 (0)
02
Detect active (1)
29
L0 to L1 (1)
03
Detect active (2)
2A
L1 entry
04
Polling active (0)
2B
L1 idle (0)
05
Polling active (1)
2C
L1 idle (1)
06
Polling config (0)
2D
L0 to L2 (0)
07
Polling config (1)
2E
L0 to L2 (1)
08
Polling compliance
2F
L2 entry
09
Configuration link width start (0)
30
L2 idle (0)
0A
Configuration link width start (1)
31
L2 idle (1)
0B
Configuration link width accept (0)
32
Recovery lock (0)
0C
Configuration link width accept (1)
33
Recovery lock (1)
0D
Configuration lane number wait (0)
34
Recovery lock (2)
0E
Configuration lane number wait (1)
35
Recovery cfg (0)