Freescale Semiconductor Reference Design System for MPC8308 MPC8308-RDB MPC8308-RDB Manual Do Utilizador
Códigos do produto
MPC8308-RDB
PCI Express Interface Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
14-64
Freescale Semiconductor
the Rx link of PHY. At a given time, either N_FTS or N_FTS_COM value is used based on the setting of
common clock configuration bit in the configuration space.
common clock configuration bit in the configuration space.
The fields of the PCI Express N_FTS Control Register are described in
14.4.6.3
PCI Express ACK Replay Timeout Register (PEX_ACKRPLY_TO)
The PCI Express ACK Replay Timeout Register, shown in
values for ACK DLLP transmission and reception in the DLL. Ack receive timeout is termed as Replay
timeout since TLPs are retransmitted after this timeout. Both values should be in terms of system clock
cycles number and have to be set based on Max-Payload-size and operating link width as specified by the
protocol.
timeout since TLPs are retransmitted after this timeout. Both values should be in terms of system clock
cycles number and have to be set based on Max-Payload-size and operating link width as specified by the
protocol.
Ack time-out will also depend upon ASPM L0s enabling for the Tx link of the device. The PCI Express
controller implements a look-up table for automatic updates of the ack and replay time-out values, based
on max-payload size, link_width and ASPM L0s enabled information. There for the reset value of this
register may be different that shown in the figure. The automatic updating of these values will be disabled
upon the first write to this register assuming that the software will take care of the updates based on the
above factors from then on.
controller implements a look-up table for automatic updates of the ack and replay time-out values, based
on max-payload size, link_width and ASPM L0s enabled information. There for the reset value of this
register may be different that shown in the figure. The automatic updating of these values will be disabled
upon the first write to this register assuming that the software will take care of the updates based on the
above factors from then on.
Offset 0x41C
Access: R/W
31
16
15
8
7
0
R
—
N_FTS_COM
N_FTS
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Figure 14-78. PCI Express N_FTS Control Register
Table 14-76. PCI Express N_FTS Control Register Fields Description
Bits
Name
Description
31–16
—
Reserved
15–8
N_FTS_COM Number of fast training sequence ordered sets in common clock mode. This is the number of Fast
training sequence (FTS) ordered sets that the PHY requires to enable its Rx circuits to achieve bit and
symbol lock and come out of ASPM L0s link power state when devices on either side of the link use
common reference clock. This N_FTS value is advertised by the PCI Express controller to the remote
device during link training if the common clock configuration bit in configuration space is set.
symbol lock and come out of ASPM L0s link power state when devices on either side of the link use
common reference clock. This N_FTS value is advertised by the PCI Express controller to the remote
device during link training if the common clock configuration bit in configuration space is set.
7–0
N_FTS
Number of Fast Training Sequence ordered sets. This is the number of fast training sequence (FTS)
ordered sets that PHY requires to enable its Rx circuits to achieve bit and symbol lock and come out of
ASPM L0s link power state. This N_FTS value is advertised by the PCI Express controller to the remote
device during link training. Its value has to be calculated based on the L0s_exit latency time required
by the PHY layer circuits.
ordered sets that PHY requires to enable its Rx circuits to achieve bit and symbol lock and come out of
ASPM L0s link power state. This N_FTS value is advertised by the PCI Express controller to the remote
device during link training. Its value has to be calculated based on the L0s_exit latency time required
by the PHY layer circuits.
Offset 0x438
Access: R/W
31
27 26
13 12
0
R
—
ACKRTV
ACKLTV
W
Reset 0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
1
0
0
1
0
0
0
0
0
1
0
0
1
0
0
0
0
Figure 14-79. PCI Express ACK Replay Timeout Register