Freescale Semiconductor MSC8156 Evaluation Module MSC8156EVM MSC8156EVM Manual Do Utilizador

7-2

  

Freescale Semiconductor

The clock generation components and clock scheme are shown in Figure 7-1.

Each PLL uses its input clock to generate a fast clock that is synchronized to the input clock. The 
fast clock is distributed to each of the clock dividers to generate the clocks that are distributed to 
the system blocks. The clock circuits are locked, according to the selected clock mode, when the 
first stage of the system reset configuration is done (reset configuration is controlled by the 
RESET block). The clock circuits are initialized after the first phase of the reset configuration, 
when the low part of the reset configuration word is loaded, according to the selected clock 
mode.

Figure 7-1.  MSC8156 Clock Scheme

CLKIN

DIV

PLL0

PLL1

SerDes1 PLL

SerDes1_REF_CLK

SERDES1CLK

SerDes PLL = SerDes Clock

Note: The source for CLKOUT is selected at reset via the Reset Configuration Word (RCW). See Chapter 5, Reset for details.

SerDes2 PLL

SerDes2_REF_CLK

SERDES2CLK

SerDes PLL = SerDes Clock

DSP Core Subsystem 0

HSSI Subsystem

QUICC Engine Subsystem

MAPLE-B Subsystem

DDR1 Controller

CLASS Subsystem

PLL 0 clk

0
1

PLL 0 clk

PLL 1 clk

DIV

PLL 0 clk

0
1

PLL 1 clk

DIV

PLL 0 clk

0
1

PLL 1 clk

DIV

PLL 0 clk

0
1

PLL 1 clk

DDR2 Controller

DIV

PLL 0 clk

0
1

PLL 2 clk

DIV

PLL 0 clk

0
1

PLL 2 clk

DIV

PLL 0 clk

0
1

PLL 2 clk

PLL 1 clk

PLL 2 clk

DSP Core Subsystem 1

DSP Core Subsystem 2

DSP Core Subsystem 3

DSP Core Subsystem 4

DSP Core Subsystem 5

PLL2