Freescale Semiconductor MSC8156 Evaluation Module MSC8156EVM MSC8156EVM Manual Do Utilizador
Códigos do produto
MSC8156EVM
Clock Generation Components and Modes
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
7-3
The MSC8156 clock modes are listed in Table 7-1.
Notes: 1.
The color of each cell, states which PLL drives its clock domain. PLL 0 is red, PLL1 is yellow, and PLL2 is blue
with white lettering.
with white lettering.
2.
In clock modes 1 and 37, PLL1 is not used. In order to save power and reduce noise, this PLL should be disabled
by setting bit 7 of RCW low (for RCW details, see Chapter 5, Reset).
by setting bit 7 of RCW low (for RCW details, see Chapter 5, Reset).
CLK_OUT pin can be driven from either PLL with selection determined by the value of
RCWLR[CLKO] (bits 31–30 of the low part of the reset configuration word—for details, see
Chapter 5, Reset). The possible CLK_OUT frequencies are listed in Table 7-2.
RCWLR[CLKO] (bits 31–30 of the low part of the reset configuration word—for details, see
Chapter 5, Reset). The possible CLK_OUT frequencies are listed in Table 7-2.
Table 7-1. MSC8156 Clock Modes
Mode
CLKIN
PLL0
PLL1
PLL2
CLASS
DSP Core
Subsystems
HSSI
QUICC
Engine
Subsystem
MAPLE-B
DDR1
DDR2
0
100
900
1000
800
500
1000
333
500
450
800
800
1
66.67
800
0
667
400
800
267
400
400
667
667
4
100
900
1000
667
500
1000
333
450
450
667
667
19
100
900
1000
800
450
1000
333
500
450
800
800
21
100
900
1000
667
450
1000
333
450
450
667
667
36
100
900
1000
800
500
1000
333
500
450
800
267
37
66.67
800
0
667
400
800
267
400
400
667
267
39
100
900
1000
667
500
1000
333
450
450
667
222
45
100
900
1000
667
450
1000
333
450
450
667
222
Table 7-2. MSC8156 CLK_OUT Frequencies
Mode
PLL0
PLL1
PLL2
CLK_OUT from PLL0
CLK_OUT from PLL1
CLK_OUT from PLL2
0
900
1000
800
75
100
80
1
800
0
667
66.67
6.7
66.67
4
900
1000
667
75
100
66.67
19
900
1000
800
75
100
80
21
900
1000
667
75
100
66.67
36
900
1000
800
75
100
80
37
800
0
667
66.67
6.7
66.67
39
900
1000
667
75
100
66.67
45
900
1000
667
75
100
66.67