Freescale Semiconductor MSC8156 Evaluation Module MSC8156EVM MSC8156EVM Manual Do Utilizador
Códigos do produto
MSC8156EVM
Detailed Register Descriptions
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
8-35
8.2.22
General Interrupt Enable Register 1 (GIER1_x)
GIER1_[0–5] includes interrupt enable bits of for the interrupts defined in GIR1 for cores 0–5.
The register is reset by a hard reset event. All bits are cleared by reset. Write accesses to this
register can only be performed in supervisor mode
The register is reset by a hard reset event. All bits are cleared by reset. Write accesses to this
register can only be performed in supervisor mode
.
GIER1_0
‘General Interrupt Enable Register 1 for Cores 0–5
Offset 0x84
GIER1_1
Offset 0x88
GIER1_2
Offset 0x8C
GIER1_3
Offset 0x90
GIER1_4
Offset 0x94
GIER1_5
Offset 0x98
Bit
31
30
29
28
27
26
25
24
SWT7_EN_n
SWT6_EN_n
SWT5_EN_n
SWT4_EN_n
SWT3_EN_n
SWT2_EN_n
SWT1_EN_n
SWT0_EN_n
Type
R/W
Reset
1
1
1
1
1
1
1
1
Bit
23
22
21
20
19
18
17
16
O2M1_ERR_EN
_n
O2M0_ERR_EN
_n
—
DMA_ERR_EN_
n
CE_IECC_EN_n CE_DECC_EN_
n
—
TDM_P0ECC_
EN_n
Type
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
—
Type
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
TDM3_TERR_
EN_n
TDM3_RERR_
EN_n
TDM2_TERR_
EN_n
TDM2_RERR_
EN_n
TDM1_TERR_
EN_n
TDM1_RERR_
EN_n
TDM0_TERR_
EN_n
TDM0_RERr_
EN_n
Type
R/W
Reset
0
0
0
0
0
0
0
0
Table 8-22. GIER1_n Bit Descriptions
Name
Reset
Description
Settings
SWT7_EN_n
31
0
SWT 7 Interrupt Enable
0
Interrupt disabled
1
Interrupt enabled
SWT6_EN_n
30
0
SWT 6 Interrupt Enable
0
Interrupt disabled
1
Interrupt enabled
SWT5_EN_n
29
0
SWT 5 Interrupt Enable
0
Interrupt disabled
1
Interrupt enabled
SWT4_EN_n
28
0
SWT 4 Interrupt Enable
0
Interrupt disabled
1
Interrupt enabled
SWT3_EN_n
27
0
SWT 3 Interrupt Enable
0
Interrupt disabled
1
Interrupt enabled
SWT2_EN_n
26
0
SWT 2 Interrupt Enable
0
Interrupt disabled
1
Interrupt enabled