Freescale Semiconductor MSC8156 Evaluation Module MSC8156EVM MSC8156EVM Manual Do Utilizador
Códigos do produto
MSC8156EVM
MSC8156 Reference Manual, Rev. 2
8-36
Freescale
Semiconductor
General Configuration Registers
SWT1_EN_n
25
0
SWT 1 Interrupt Enable
0
Interrupt disabled
1
Interrupt enabled
SWT0_EN_n
24
0
SWT 0 Interrupt Enable
0
Interrupt disabled
1
Interrupt enabled
O2M1_ERR_EN
_n
23
23
0
O2M1 Error Interrupt Enable
0
Interrupt disabled
1
Interrupt enabled
O2M0_ERR_EN
_n
22
22
0
O2M0 Error Interrupt Enable
0
Interrupt disabled
1
Interrupt enabled
—
21
0
Reserved. Write to zero for future compatibility.
DMA_ERR_EN_
n
20
0
DMA Error Interrupt Enable
0
Interrupt disabled
1
Interrupt enabled
CE_IECC_EN_n
19
0
ECC Error Interrupt of the QUICC Engine IMEM
Enable
Enable
0
Interrupt disabled
1
Interrupt enabled
CE_DECC_EN_
n
18
0
ECC Error Interrupt of the QUICC Engine DRAM
Enable
Enable
0
Interrupt disabled
1
Interrupt enabled
—
17
0
Reserved. Write to zero for future compatibility.
TDM_P0ECC_E
N_n
16
0
Parity Error Interrupt of TDM[0–3] Enable
0
Interrupt disabled
1
Interrupt enabled
—
15–8
0
Reserved. Write to zero for future compatibility.
TDM3_TER_EN
_n
7
0
TDM3 Transmit Error Interrupt Enable
0
Interrupt disabled
1
Interrupt enabled
TDM3_RER_EN
_n
6
0
TDM3 Receive Error Interrupt Enable
0
Interrupt disabled
1
Interrupt enabled
TDM2_TER_EN
_n
5
0
TDM2 Transmit Error Interrupt Enable
0
Interrupt disabled
1
Interrupt enabled
TDM2_RER_EN
_n
4
0
TDM2 Receive Error Interrupt Enable
0
Interrupt disabled
1
Interrupt enabled
TDM1_TER_EN
_n
3
0
TDM1 Transmit Error Interrupt Enable
0
Interrupt disabled
1
Interrupt enabled
TDM1_RER_EN
_n
2
0
TDM1 Receive Error Interrupt Enable
0
Interrupt disabled
1
Interrupt enabled
TDM0_TER_EN
_n
1
0
TDM0 Transmit Error Interrupt Enable
0
Interrupt disabled
1
Interrupt enabled
TDM0_RER_EN
_n
0
0
TDM0 Receive Error Interrupt Enable
0
Interrupt disabled
1
Interrupt enabled
Table 8-22. GIER1_n Bit Descriptions
Name
Reset
Description
Settings