Galil DMC-1700 Manual Do Utilizador
DMC-1700/1800
Chapter 4 - Software Tools and Communications • 73
Resetting the PC to DMC FIFO - To reset the output FIFO, write data to address N+8 where bit 2 is high and all other
bits are low.
bits are low.
Resetting the DMC to PC FIFO - To reset the input FIFO, write data to address N+8 where bit 1 is high and all other
bits are low.
bits are low.
Resetting the Controller - Resetting the FIFO is useful for emergency resets or Abort. For example, to reset the
controller, clear the FIFO, then send the RS command. If the controller is not responding, it may be necessary to provide
a hardware reset to the controller. This can be accomplished by writing data to address N+8 where bit 7 is high.
controller, clear the FIFO, then send the RS command. If the controller is not responding, it may be necessary to provide
a hardware reset to the controller. This can be accomplished by writing data to address N+8 where bit 7 is high.
When the FIFO is reset, all FIFO configuration is lost and must be rewritten.
Reset Register at N+8
Status Bit
Purpose
Logic State
Meaning
7 WRITE
1
Reset
Controller
2
WRITE
1
Reset PC_to_DMC FIFO
1
WRITE
1
Reset DMC_to_PC FIFO
Dual Port RAM (DPRAM) access for reading the Data Record
Immediate access to any or all bytes of the data record can be accessed by reading directly from the Dual Port RAM
registers. The starting address for the dual port RAM is stored at BAR0 of the PCI configuration space. The following
memory map describes the data record registers and the associated controller information.
registers. The starting address for the dual port RAM is stored at BAR0 of the PCI configuration space. The following
memory map describes the data record registers and the associated controller information.
Note: the same procedure for “freezing” the data record (as with Secondary FIFO) should be followed to ensure that all
data of the data record is from the same sample period.
data of the data record is from the same sample period.
DMA / Secondary FIFO / DPRAM Memory Map
ADDR TYPE ITEM
00-01 UW sample
number
02
UB
general input block 0 (inputs 1-8)
03
UB
general input block 1 (inputs 9-16)
04
UB
general input block 2 (inputs 17-24)
05
UB
general input block 3 (inputs 25-32)
06
UB
general input block 4 (inputs 33-40)
07
UB
general input block 5 (inputs 41-48)
08
UB
general input block 6 (inputs 49-56)
09
UB
general input block 7 (inputs 57-64)
10
UB
general input block 8 (inputs 65-72)
11
UB
general input block 9 (inputs 73-80)
12
UB
general output block 0 (outputs 1-8)
13
UB
general output block 1 (outputs 9-16)
14
UB
general output block 2 (outputs 17-24)
15
UB
general output block 3 (outputs 25-32)
16
UB
general output block 4 (outputs 33-40)
17
UB
general output block 5 (outputs 41-48)