Справочник Пользователя для Intel SE7520JR2
Intel® Server Board SE7520JR2
Platform Management
Revision 1.0
C78844-002
131
time, the LED will turn off. If the LED is on, a button press or IPMI Chassis Identify command
turns off the LED.
turns off the LED.
Upon assertion of the chassis identify button, a SEL event is generated by the chassis identity
sensor button. The event attributes are: Sensor Type code - 14h (Button) and Sensor Specific
offset - 1h.
sensor button. The event attributes are: Sensor Type code - 14h (Button) and Sensor Specific
offset - 1h.
5.3.6
Secure Mode Operation
The mBMC handles the secure mode feature, which allows the control panel power and reset
buttons to be protected against unauthorized use or access. Secure mode is a signal from the
keyboard controller and is asserted when the keyboard controller is in a locked state. Power
and reset buttons are locked and a security violation event is generated if these buttons are
pressed while secure mode is active.
buttons to be protected against unauthorized use or access. Secure mode is a signal from the
keyboard controller and is asserted when the keyboard controller is in a locked state. Power
and reset buttons are locked and a security violation event is generated if these buttons are
pressed while secure mode is active.
Secure Mode state is cleared whenever the System is powered down, the Set Chassis
Capabilities command is issued to change the Secure Mode state, or the FP_LOCK signal is
de-asserted.
Capabilities command is issued to change the Secure Mode state, or the FP_LOCK signal is
de-asserted.
5.3.7
Baseboard Fan Control
Fan control is performed by two pulse width modulator (PWM) outputs on the LM93. The 3-pin
CPU fan headers (J5F2, J7F1) are not controlled. These operate at a constant speed. The
mBMC initializes the LM93 to control fan speeds based on temperature.
CPU fan headers (J5F2, J7F1) are not controlled. These operate at a constant speed. The
mBMC initializes the LM93 to control fan speeds based on temperature.
The LM93 controls the actual fan speeds based on temperature measurements according to a
built-in table. The table itself is loaded as part of the SDR package according to which system
configuration is used. In addition, BIOS passes in certain temperature data to the LM93 during
POST.
built-in table. The table itself is loaded as part of the SDR package according to which system
configuration is used. In addition, BIOS passes in certain temperature data to the LM93 during
POST.
5.3.8
mBMC Peripheral SMBus
The mBMC implements a single private SMBus called the peripheral SMBus. The mBMC
supports master-only mode for this SMBus. External agents must use the mBMC’s Master
Write/Read I
supports master-only mode for this SMBus. External agents must use the mBMC’s Master
Write/Read I
2
C command if they require direct communication with a device on this bus.
5.3.9 Watchdog
Timer
The mBMC implements a fully IPMI 1.5 compatible watchdog timer. See the IPMI 1.5
specification for details on watchdog timer configuration.
specification for details on watchdog timer configuration.
5.3.10
System Event Log (SEL)
The mBMC implements the logical System Event Log (SEL) device as specified in the Intelligent
Platform Management Interface Specification, Version 1.5. The SEL is accessible via all
channels. In this way, the SEL information can be accessed through out-of-band interfaces
while the system is down. The mBMC supports a maximum SEL size of 92 entries.
Platform Management Interface Specification, Version 1.5. The SEL is accessible via all
channels. In this way, the SEL information can be accessed through out-of-band interfaces
while the system is down. The mBMC supports a maximum SEL size of 92 entries.
If an Intel® Management Module is installed in the server, the mBMC System Event Log is not
accessible and is replaced by the Intel Management Module System Event Log.
accessible and is replaced by the Intel Management Module System Event Log.