Справочник Пользователя для Intel SE7520JR2
Intel® Server Board SE7520JR2
Functional Architecture
Revision 1.0
C78844-002
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BSP and starts executing from the reset vector (F000:FFF0h). A processor that does not
perform the role of BSP is referred to as an application processor (AP).
perform the role of BSP is referred to as an application processor (AP).
The BSP is responsible for executing the BIOS power-on self-test (POST) and preparing the
machine to boot the operating system. At boot time, the system is in virtual wire mode and the
BSP alone is programmed to accept local interrupts (INTR driven by programmable interrupt
controller (PIC) and non-maskable interrupt (NMI)).
machine to boot the operating system. At boot time, the system is in virtual wire mode and the
BSP alone is programmed to accept local interrupts (INTR driven by programmable interrupt
controller (PIC) and non-maskable interrupt (NMI)).
As a part of the boot process, the BSP enables the application processor. When enabled, the
AP programs its Memory Type Range Registers (MTRRs) to be identical to those of the BSP.
The AP executes a halt instruction with its local interrupts disabled. If the BSP determines that
an AP exists that is a lower-featured processor or that has a lower value returned by the CPUID
function, the BSP switches to the lowest-featured processor in the system.
AP programs its Memory Type Range Registers (MTRRs) to be identical to those of the BSP.
The AP executes a halt instruction with its local interrupts disabled. If the BSP determines that
an AP exists that is a lower-featured processor or that has a lower value returned by the CPUID
function, the BSP switches to the lowest-featured processor in the system.
3.1.8
CPU Thermal Sensors
The CPU temperature will be indirectly measured via thermal diodes. These are monitored by
the LM93 sensor monitoring device. The mBMC configures the LM93 to monitor these sensors.
The temperatures are available via mBMC IPMI sensors.
the LM93 sensor monitoring device. The mBMC configures the LM93 to monitor these sensors.
The temperatures are available via mBMC IPMI sensors.
3.1.9
Processor Thermal Control Sensor
The Intel Xeon processors generate a signal to indicate throttling due to a processor over temp
condition. The mBMC implements an IPMI sensor that provides the percentage of time a
processor has been throttled over the last 1.46 seconds. Baseboard management forces a
thermal control condition when reliable system operation requires reduced power consumption.
condition. The mBMC implements an IPMI sensor that provides the percentage of time a
processor has been throttled over the last 1.46 seconds. Baseboard management forces a
thermal control condition when reliable system operation requires reduced power consumption.
3.1.10
Processor Thermal Trip Shutdown
If a thermal overload condition exists (thermal trip), the processor outputs a digital signal that is
monitored by the baseboard management sub-system. A thermal trip is a critical condition and
indicates that the processor may become damaged if it continues to run. To help protect the
processor, the management controller automatically powers off the system. In addition the
System Status LED will change to Amber and the error condition will be logged to the System
Event Log (SEL).
monitored by the baseboard management sub-system. A thermal trip is a critical condition and
indicates that the processor may become damaged if it continues to run. To help protect the
processor, the management controller automatically powers off the system. In addition the
System Status LED will change to Amber and the error condition will be logged to the System
Event Log (SEL).
If either the Intel Management Module Professional Edition or Advanced Edition is present in the
system, the Fault LED fro the affected processor will also be illuminated.
system, the Fault LED fro the affected processor will also be illuminated.
3.1.11 Processor
IERR
The IERR signal is asserted by the processor as the result of an internal error. The mBMC
configures the LM93 device to monitor this signal. When this signal is asserted, the mBMC
generates a processor IERR event.
configures the LM93 device to monitor this signal. When this signal is asserted, the mBMC
generates a processor IERR event.
3.2 Intel® E7520 Chipset
The architecture of the Server Board SE7520JR2 is designed around the Intel E7520 chipset.
The chipset consists of three components that together are responsible for providing the
interface between all major sub-systems found on the baseboard, including the processor,
memory, and I/O sub-systems. These components are:
The chipset consists of three components that together are responsible for providing the
interface between all major sub-systems found on the baseboard, including the processor,
memory, and I/O sub-systems. These components are: