Справочник Пользователя для Intel SE7520JR2
Functional Architecture
Intel® Server Board SE7520JR2
Revision 1.0
C78844-002
32
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Memory Controller Hub (MCH)
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I/O Controller Hub (ICH5-R)
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PCI-X Hub (PXH)
The following sub-sections provide an overview of the primary functions and supported features
of each chipset component as they are used on the Server Board SE7520JR2. Later sections in
this chapter provide more detail on the implementation of the sub-systems.
of each chipset component as they are used on the Server Board SE7520JR2. Later sections in
this chapter provide more detail on the implementation of the sub-systems.
3.2.1
Memory Controller Hub (MCH)
The MCH integrates four functions into a single 1077-ball FC-BGA package:
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Front Side Bus
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Memory Controller
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PCI-Express Controller
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Hub Link Interface
3.2.1.1
Front Side Bus (FSB)
The E7520 MCH supports either single or dual processor configurations using 800MHz FSB
Intel Xeon processors. The MCH supports a base system bus frequency of 200 MHz. The
address and request interface is double pumped to 400 MHz while the 64-bit data interface
(+ parity) is quad pumped to 800 MHz. This provides a matched system bus address and data
bandwidths of 6.4 GB/s
Intel Xeon processors. The MCH supports a base system bus frequency of 200 MHz. The
address and request interface is double pumped to 400 MHz while the 64-bit data interface
(+ parity) is quad pumped to 800 MHz. This provides a matched system bus address and data
bandwidths of 6.4 GB/s
3.2.1.2
MCH Memory Sub-System Overview
The MCH provides an integrated memory controller for direct connection to two channels of
registered DDR-266, DDR-333 or DDR2-400 memory (stacked or unstacked). Peak theoretical
memory data bandwidth using DDR266 technology is 4.26 GB/s and 5.33 GB/S for DDR333
technology. For DDR2-400 technology, this increases to 6.4 GB/s.
registered DDR-266, DDR-333 or DDR2-400 memory (stacked or unstacked). Peak theoretical
memory data bandwidth using DDR266 technology is 4.26 GB/s and 5.33 GB/S for DDR333
technology. For DDR2-400 technology, this increases to 6.4 GB/s.
Several RASUM (Reliability, Availability, Serviceability, Usability, and Manageability) features
are provided by the E7520 MCH memory interface.
are provided by the E7520 MCH memory interface.
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Memory mirroring allows two copies of all data in the memory subsystem to be maintained
(one on each channel).
(one on each channel).
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DIMM sparing allows one DIMM per channel to be held in reserve and brought on-line if
another DIMM in the channel becomes defective. DIMM sparing and memory mirroring are
mutually exclusive.
another DIMM in the channel becomes defective. DIMM sparing and memory mirroring are
mutually exclusive.
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Hardware periodic memory scrubbing, including demand scrub support.
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Retry on uncorrectable memory errors.
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x4 SDDC for memory error detection and correction of any number of bit failures in a single
x4 memory device.
x4 memory device.
3.2.1.3 PCI
Express
The E7520 MCH is the first Intel chipset to support the new PCI Express* high-speed serial I/O
interface for superior I/O bandwidth. The scalable PCI Express interface complies with the PCI
Express Interface Specification, Rev 1.0a. On the Server Board SE7520JR2, two of the three
available x8 PCI Express interfaces are used, each with a maximum theoretical bandwidth of 4
interface for superior I/O bandwidth. The scalable PCI Express interface complies with the PCI
Express Interface Specification, Rev 1.0a. On the Server Board SE7520JR2, two of the three
available x8 PCI Express interfaces are used, each with a maximum theoretical bandwidth of 4