Справочник Пользователя для AMD LX 900@1.5W
AMD Geode™ LX Processors Data Book
129
CPU Core Register Descriptions
33234H
5.5.2.21 Debug Management Interrupt (DMI) Control Register
MSR Address
MSR Address
00001302h
Type
R/W
Reset Value
00000000_00000000h
DMI Control Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
DMI_TF
DMI
_
S
T
ALL
DMM_SUSP
DM
I_
T
S
S
DMM_CA
CH
E
DMI_IC
E
B
P
DMI_DBG
DM
I_
E
X
T
DMI_GPF
DMI_
INST
DMI Control Register Bit Descriptions
Bit
Name
Description
63:10
RSVD
Reserved. Write as read.
9
DMI_TF
DMI Trap Flag.
0: Disable DMI single stepping.
1: If DMI_STALL (bit 8) is 0, DMI occurs after the successful execution of each instruc-
1: If DMI_STALL (bit 8) is 0, DMI occurs after the successful execution of each instruc-
tion. If DMI_STALL is 1, debug stall occurs after the successful execution of each
instruction.
instruction.
8
DMI_STALL
DMI Stall.
0: If not in DMM, DMI conditions cause DMIs.
1: DMI conditions cause a debug stall.
1: DMI conditions cause a debug stall.
7
DMM_SUSP
Enable SUSP# during DMM. Enable SUSP# during DMM mode.
0: Disable.
1: Enable.
1: Enable.
6
DMI_TSS
Task Switch Debug Fault Control.
0: Task switch debug faults cause debug exceptions.
1: Task switch debug exceptions cause DMIs when not in DMM.
1: Task switch debug exceptions cause DMIs when not in DMM.
5
DMM_CACHE
Cache Control during DMM.
0: Do not change CR0 CD and NW bits when entering DMM.
1: Set CR0, CD and NW bits when entering DMM
1: Set CR0, CD and NW bits when entering DMM
.
See Table 5-10 "CR0 Bit Descriptions" on page 96 for CD and NW bit descriptions.
4
DMI_ICEBP
Enable DMIs on ICEBP (F1) Instructions.
0: Disable.
1: Enable.
1: Enable.
3
DMI_DBG
Enable Replacing Debug Exceptions as DMIs.
0: Disable.
1: Enable.
1: Enable.
2
DMI_EXT
Enable External TDBGI Pin. Enable DMIs caused by the TDBGI pin (ball AB2) when not
in DMM.
in DMM.
0: Disable.
1: Enable.
1: Enable.