Справочник Пользователя для AMD LX 900@1.5W
130
AMD Geode™ LX Processors Data Book
CPU Core Register Descriptions
33234H
5.5.2.22 Temporary MSRs
Temporary 0 MSR (TEMP0_MSR)
Temporary 1 MSR (TEMP1_MSR)
Temporary 2 MSR (TEMP2_MSR)
Temporary 3 MSR (TEMP3_MSR)
1
DMI_GPF
DMI General Protection Faults. When enabled and not in DMM mode, allow general
protection faults to generate DMIs.
protection faults to generate DMIs.
0: Disable.
1: Enable.
1: Enable.
0
DMI_INST
DMI Instructions. Enable DMI instructions DMINT and RDM. If not enabled, executing a
DMI instruction generates an invalid operation fault.
DMI instruction generates an invalid operation fault.
0: Disable.
1: Enable.
1: Enable.
DMI Control Register Bit Descriptions (Continued)
Bit
Name
Description
MSR Address
00001310h
Type
R/W
Reset Value
xxxxxxxx_xxxxxxxxh
MSR Address
00001311h
Type
R/W
Reset Value
xxxxxxxx_xxxxxxxxh
MSR Address
00001312h
Type
R/W
Reset Value
xxxxxxxx_xxxxxxxxh
MSR Address
00001313h
Type
R/W
Reset Value
xxxxxxxx_xxxxxxxxh
TEMPx_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
TEMPx
TEMPx_MSR Bit Descriptions
Bit
Name
Description
63:32
RSVD
Reserved. Write as read.
31:0
TEMPx
Temporary x. Used by microcode, usually for holding operands for address calculations.