Справочник Пользователя для National Instruments NI PXIe-6672
Chapter 3
Hardware Overview
3-10
ni.com
Figures 3-3 and 3-4 summarize the routing features of the NI PXIe-6672.
The remainder of this chapter details the capabilities and constraints of
the routing architecture.
The remainder of this chapter details the capabilities and constraints of
the routing architecture.
Figure 3-3. High-Level Schematic of NI PXIe-6672 Signal Routing Architecture
PFI 0
DDS
PXI_CLK10
÷2
N
÷2
M
PFI 0
DDS
PXI_CLK10
÷2
N
÷2
M
Selection
Circuitry
Selection
Circuitry
PFI 0
PFI 1
PFI 5
Selection
Circuitry
Selection
Circuitry
Selection
Circuitry
Selection
Circuitry
Selection
Circuitry
PXI_TRIG 0
PXI_TRIG 1
PXI_TRIG 7
Selection
Circuitry
Selection
Circuitry
3
SYNCHRONIZATION
CLOCKS for PFI<0..5>
28
SOURCE
*
3
*
PXI_STAR<0..16>,
PXI_TRIG<0..7>,
PFI<0..5>, and
Software Trigger are
routed to SOURCE
of each Selection
Circuitry block.
PXI_TRIG<0..7>,
PFI<0..5>, and
Software Trigger are
routed to SOURCE
of each Selection
Circuitry block.
SYNCHRONIZATION
CLOCKS for
PXI_STAR<0..16> and
PXI_TRIG<0..7>
PXI_STAR 0
PXI_STAR 1
PXI_STAR 16
CLKIN