Справочник Пользователя для National Instruments PCI-1428
Chapter 3
Hardware Overview
3-2
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Figure 3-1. PCI-1428 Block Diagram
Camera Link and PCI-1428
The PCI-1428 supports the Camera Link Base configuration, as well as the
8-bit
8-bit
× 4 mode of the Camera Link Medium configuration.
Base Configuration
The Camera Link Base configuration places 24 data bits and four enable
signals (Frame Valid, Line Valid, Data Valid, and a spare) on a single
Channel Link part and cable.
signals (Frame Valid, Line Valid, Data Valid, and a spare) on a single
Channel Link part and cable.
The Base configuration includes asynchronous serial transmission as well
as four digital camera control lines for controlling exposure time, frame
rates, and other camera control signals. These four control lines are
as four digital camera control lines for controlling exposure time, frame
rates, and other camera control signals. These four control lines are
Data
26-Pin MDR Connector
Channel
Link
Receiver
Enables
Pixel
Clock
Camera
Control
UART
PCI Bus
PCI Interface
and
Scatter-Gather
DMA Controllers
Data
IMAQ SDRAM
Interface
Synchronous Dynamic RAM
Advanced
Triggering
Triggering
and Timing
Acquisition, Scaling,
ROI, and Control
External Triggers
Pixel Clock and Camera Enables
RTSI Bus
LUT
LUT
Data
Data
Differential
Converter
68-Pin VHDCI
Serial
Control
Enables
Pixel
Clock
Channel
Link
Receiver
Data