Справочник Пользователя для National Instruments PCI-1428

Many digital cameras transfer multiple taps, or channels, of data 
simultaneously to increase the frame rate of the camera. However, the data 
in each tap may not be transferred in the traditional top-left to bottom-right 
direction. Also, the taps may not transfer data in the same direction.

The multiple-tap data formatting circuitry on the PCI-1428 can reorder the 
data from up to four taps. The data from each tap can be independently 
scanned either from left-to-right or right-to-left and top-to-bottom or 
bottom-to-top.

For your convenience, data reformatting instructions for these cameras have been 

preprogrammed into the camera files.

The PCI-1428 has 16 MB of onboard high-speed synchronous dynamic 
RAM (SDRAM). The PCI-1428 uses the onboard RAM as a FIFO buffer 
to ensure acquisition. Even when the data rate from the camera exceeds PCI 
throughput, you can acquire without interruption until the onboard RAM is 
full.

The trigger control and mapping circuitry routes, monitors, and drives 
the external and RTSI bus trigger lines. You can configure each line to start 
an acquisition on a rising or falling edge and drive each line asserted or 
unasserted, much like a digital I/O line. You can also map pulses from the 
high-speed timing circuitry or many of the PCI-1428 status signals to these 
trigger lines. Four external and four RTSI bus triggers (all of which are 
programmable for polarity and direction) are available for simultaneous 
use.

Built from high-speed counters, the high-speed timing circuitry on the 
PCI-1428 can generate precise real-time control signals for your camera. 
Map the output of this circuitry to a trigger line to provide accurate pulses 
and pulse trains. Use these control signals to control exposure time and 
frame rate.

For your convenience, the external control for cameras that support it has been 

preprogrammed into the camera file. You can use MAX to specify the frequency and