Справочник Пользователя для National Instruments PCI-1428
Chapter 3
Hardware Overview
© National Instruments Corporation
3-3
configured in the camera file to generate precise timing signals for
controlling digital camera acquisition.
controlling digital camera acquisition.
Base configuration includes the following bit allocations:
•
8-bit
× 1, 2, and 3 taps (channels)
•
10-bit
× 1 and 2 taps
•
12-bit
× 1 and 2 taps
•
14-bit
× 1 tap
•
16-bit
× 1 tap
•
24-bit RGB
Medium Configuration
The PCI-1428 supports the 8-bit
× 4 tap of the Camera Link Medium
configuration. The Medium configuration requires using both connectors.
This configuration allows for more data throughput by offering
two synchronized data streams between the camera and the PCI-1428.
This configuration allows for more data throughput by offering
two synchronized data streams between the camera and the PCI-1428.
Data Transmission
A 28-to-4 serializing Channel Link chip drives the data and camera enable
signals across the Camera Link cable, and the camera’s pixel clock controls
the Channel Link’s data transmission. The four LVDS pairs are then
deserialized by another Channel Link chip on the PCI-1428.
signals across the Camera Link cable, and the camera’s pixel clock controls
the Channel Link’s data transmission. The four LVDS pairs are then
deserialized by another Channel Link chip on the PCI-1428.
Note
Exact timing of camera and image acquisition device communication is camera
dependent. The Specifications of the Camera Link Interface Standard for Digital Cameras
and Frame Grabbers manual fully explains the Camera Link timing requirements.
and Frame Grabbers manual fully explains the Camera Link timing requirements.
LUTs
The PCI-1428 offers two 64 KB
× 16-bit lookup tables (LUTs) that can
perform up to four 256 KB
× 8-bit LUT operations, such as contrast
enhancement, data inversion, gamma manipulation, or other nonlinear
transfer functions.
transfer functions.