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Chapter 4
Connecting Signals
© National Instruments Corporation
4-33
Figure 4-27. UPDATE* Output Signal Timing
The DACs are updated within 100 ns of the leading edge. Separate the
UPDATE* pulses with enough time that new data can be written to the DAC
latches.
UPDATE* pulses with enough time that new data can be written to the DAC
latches.
The device UI counter normally generates the UPDATE* signal unless you
select some external source. The UI counter is started by the WFTRIG
signal and can be stopped by software or the internal Buffer Counter (BC).
D/A conversions generated by either an internal or external UPDATE*
signal do not occur when gated by the software command register gate.
select some external source. The UI counter is started by the WFTRIG
signal and can be stopped by software or the internal Buffer Counter (BC).
D/A conversions generated by either an internal or external UPDATE*
signal do not occur when gated by the software command register gate.
UISOURCE Signal
Any PFI pin can externally input the UISOURCE signal, which is not
available as an output on the I/O connector. The UI counter uses
UISOURCE as a clock to time the generation of the UPDATE* signal.
You must configure the PFI pin you select as the source for UISOURCE
in the level-detection mode. You can configure the polarity selection for
the PFI pin for either active high or active low. Figure 4-28 shows the
timing requirements for UISOURCE.
available as an output on the I/O connector. The UI counter uses
UISOURCE as a clock to time the generation of the UPDATE* signal.
You must configure the PFI pin you select as the source for UISOURCE
in the level-detection mode. You can configure the polarity selection for
the PFI pin for either active high or active low. Figure 4-28 shows the
timing requirements for UISOURCE.
Figure 4-28. UISOURCE Signal Timing
t
w
= 300 to 350 ns
t
w
t
p
= 50 ns minimum
t
w
= 23 ns minimum
t
w
t
w
t
p