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Datasheet, Volume 2

243

Processor Configuration Registers 

This register defines the power-down (CKE-off) operation – power-down mode, idle 
timer and global / per rank decision.

31:13

RO

0h

12

RW-L

0b

Uncore

Global power-down (GLPDN) 
1 = When this bit is set, the power-down decision is global for 

channel. 

0 = When this bit is clear, a separate decision is taken for each 

rank.

11:8

RW-L

0h

Uncore

Power-down mode (PDWN_mode) 
Selects the mode of power-down:
0h = No Power-Down
1h = APD
2h = PPD
3h = APD+PPD
4h = Reserved
5h = Reserved
6h = PPD_DLLoff
7h = APD+PPD_DLLoff
8h–Fh = Reserved

When selecting DLL-off or APD-DLL off, DIMM MR0 

register bit 12 (PPD) must equal 0.

When selecting APD, PPD or APD-PPD DIMM MR0 

register bit 12 (PPD) must equal 1.

The value 0x0 (no power-down) is a don't care.

7:0

RW-L

00h

Uncore

Power-down idle timer (PDWN_idle_counter) 
This field defines the rank idle period in DCLK cycles that causes 

power-down entrance.