Справочник Пользователя для HP A2Y15AV

Datasheet, Volume 2

245

Processor Configuration Registers

2.14

MCHBAR Registers in Memory Controller –

Channel 1

2.14.1

TC_DBP_C1—Timing of DDR – Bin Parameters Register

This register defines the BIN timing parameters for safe logic – tRCD, tRP, tCL, tWCL,
and tRAS.

Table 2-17. MCHBAR Registers in Memory Controller – Channel 1 Register Address Map

Address

Register

Symbol

Register Name

Reset Value

Access

0–43FFh

RSVD

Reserved

4400–4403h

TC_DBP_C1

Timing of DDR – bin parameters

00146666h

RW-L

4404–4407h

TC_RAP_C1

Timing of DDR – regular access

parameters

86104344h

RW-L

4408–4427h

RSVD

Reserved

—

4428–442Bh

SC_IO_LATENCY_

IO Latency configuration

000E0000h

RW-L

442C–44AFh

RSVD

Reserved

—

44B0–44B3h

PM_PDWN_config

_C1

Power-down configuration register

00000000h

RW-L

44BC–44C7h

RSVD

Reserved

44D0–4693h

RSVD

Reserved

—

4694–4697h

TC_RFP_C1

Refresh parameters

0000980Fh

RW-L

4698–469Bh

TC_RFTP_C1

Refresh timing parameters

46B41004h

RW-L

469C–469Fh

RSVD

Reserved

00000000h

RW-L

46A0–46A3h

RSVD

Reserved

00000000h

RW-L

46A4–46A7h

TC_SRFTP_C1

Self Refresh Timing Parameters

0100B200h

RW-L

46A8–478Fh

RSVD

Reserved

—

B/D/F/Type:

0/0/0/MCHBAR MC1

Address Offset:

4400–4403h

Reset Value:

00146666h

Access:

RW-L

Size:

32 bits

BIOS Optimal Default

00h

Bit

Access

Reset

Value

RST/

PWR

Description

31:24

Reserved (RSVD)

23:16

RW-L

14h

Uncore

tRAS in DCLK cycles (tRAS)
Minimum ACT to PRE timing Range is 10 to 40 DCLK cycles.

15:12

RW-L

Uncore

Write CAS latency in DCLK cycles (tWCL)
Delay from CAS WR command to data valid on DDR pins. Range

is 5–15. The value 5 should not be programmed if the DEC_WRD

bit in TC_RWP register is set.