Техническая Спецификация для Freescale Semiconductor MC56F8006 Demo board MC56F8006DEMO MC56F8006DEMO
Модели
MC56F8006DEMO
Specifications
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
65
8.14
COP Specifications
8.15
PGA Specifications
Table 34. COP Specifications
Parameter
Symbol
Min
Typ
Max
Unit
Oscillator output frequency
LPFosc
500
1000
1500
Hz
Oscillator current consumption in partial power down mode
IDD
TBD
nA
Table 35. PGA Specifications
Parameter
Symbol
Min
Max
Unit
Digital logic inputs amplitude (_2p5 signal)
V
2p5
2.75
V
DC analog input level (@ V
DD
= avdd3p3)
PGA S/H stage enabled (BP=0)
PGA S/H stage disabled (BP=1)
V
IL
0
V
DD
V
DD
– 0.5
V
Max differential input voltage (@ Gain and V
DD
= avdd3p3)
V
DIFFMAX
(V
DD
– 1) x 0.5/gain
V
Linearity (@ voltage gain)
1x
2x
4x
8x
16x
32x
1x
2x
4x
8x
16x
32x
L
V
1 – 1/2 LSB
2 – 1/2 LSB
2 – 1/2 LSB
4 – 1 LSB
8 – 1 LSB
8 – 1 LSB
16 – 4 LSB
32 – 4 LSB
32 – 4 LSB
1 + 1/2 LSB
2 + 1/2 LSB
2 + 1/2 LSB
4 + 1 LSB
8 + 1 LSB
8 + 1 LSB
16 + 4 LSB
32 + 4 LSB
32 + 4 LSB
V/V
Gain error (@ voltage gain)
1x
2x
4x
8x
16x
32x
1x
2x
4x
8x
16x
32x
A
V
1%
V/V
Sampling frequency (pga_clk_2p5)
normal mode (pga_lp_2p5 asserted)
low power mode (pga_lp_2p5 negated)
SF
max
8
4
4
MHz
Input signal bandwidth
Motor Control mode (BP=0)
General Purpose mode (BP=1)
BW
max
PGA sampling rate/2
PGA sampling rate/8
PGA sampling rate/8
Hz
Internal voltage doubler clock frequency(pga_clk_doubler_2p5)
VD
clk
100
2000
kHz
Operating temperature
T
–40
125
o
C