Техническая Спецификация для STMicroelectronics Evaluation board for A5970AD EVALA5970AD EVALA5970AD
Модели
EVALA5970AD
DocID14661 Rev 5
13/42
A5970AD
Functional description
42
5.6
PWM comparator and power stage
This block compares the oscillator sawtooth and the error amplifier output signals to
generate the PWM signal for the driving stage.
generate the PWM signal for the driving stage.
The power stage is a highly critical block, as it functions to guarantee a correct turn ON and
turn OFF of the PDMOS. The turn ON of the power element, or more accurately, the rise
time of the current at turn ON, is a very critical parameter. At a first approach, it appears that
the faster the rise time, the lower the turn ON losses.
turn OFF of the PDMOS. The turn ON of the power element, or more accurately, the rise
time of the current at turn ON, is a very critical parameter. At a first approach, it appears that
the faster the rise time, the lower the turn ON losses.
However, there is a limit introduced by the recovery time of the recirculation diode.
In fact, when the current of the power element is equal to the inductor current, the diode
turns OFF and the drain of the power is able to go high. But during its recovery time, the
diode can be considered a high value capacitor and this produces a very high peak current,
responsible for numerous problems:
turns OFF and the drain of the power is able to go high. But during its recovery time, the
diode can be considered a high value capacitor and this produces a very high peak current,
responsible for numerous problems:
Spikes on the device supply voltage that cause oscillations (and thus noise) due to the
board parasites.
board parasites.
Turn ON overcurrent leads to a decrease in the efficiency and system reliability.
Major EMI problems.
Shorter freewheeling diode life.
The fall time of the current during turn OFF is also critical, as it produces voltage spikes (due
to the parasites elements of the board) that increase the voltage drop across the PDMOS.
to the parasites elements of the board) that increase the voltage drop across the PDMOS.
In order to minimize these problems, a new driving circuit topology has been used and the
block diagram is shown in
block diagram is shown in
. The basic idea is to change the current levels used to
turn the power switch ON and OFF, based on the PDMOS and the gate clamp status.
This circuitry allows the power switch to be turned OFF and ON quickly and addresses the
freewheeling diode recovery time problem. The gate clamp is necessary to ensure that V
freewheeling diode recovery time problem. The gate clamp is necessary to ensure that V
GS
of the internal switch does not go higher than V
GS
max. The ON/OFF Control block protects
against any cross conduction between the supply line and ground.
Figure 8. Driving circuitry