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The PCI Bridge
18
Interphase Corporation
PowerSpan Miscellaneous Registers
This group of registers includes several configuration registers for the interrupt functions,
as well as various runtime registers: mailboxes, doorbells, interrupt control/status, and
semaphores. They are mapped in the PCI memory space (base address defined in PCI
configuration register 0x14 PCIBAR1) and in the local space for the local processor (base
address 0xF0020000).
as well as various runtime registers: mailboxes, doorbells, interrupt control/status, and
semaphores. They are mapped in the PCI memory space (base address defined in PCI
configuration register 0x14 PCIBAR1) and in the local space for the local processor (base
address 0xF0020000).
Table 1-19. PowerSpan Miscellaneous Registers
Offset
Register
Description
[
0,6&B&65
0LVFHOODQHRXV&RQWURO6WDWXV5HJLVWHU
[
&/2&.B&7/
&ORFN&RQWURO5HJLVWHU
[
,ð&B&65
,ð&,QWHUIDFH&RQWURODQG6WDWXV5HJLVWHU
[&
567B&65
5HVHW&RQWURODQG6WDWXV5HJLVWHU
[
,65
,QWHUUXSW6WDWXV5HJLVWHU
[
,65
,QWHUUXSW6WDWXV5HJLVWHU
[
,(5
,QWHUUXSW(QDEOH5HJLVWHU
[&
,(5
,QWHUUXSW(QDEOH5HJLVWHU
[
,05B0%2;
,QWHUUXSW0DS5HJLVWHU 0DLOER[
[
,05B'E
,QWHUUXSW0DS5HJLVWHU 'RRUEHOO
[
,05B'0$
,QWHUUXSW0DS5HJLVWHU '0$
[&
,05B+:
,QWHUUXSW0DS5HJLVWHU +DUGZDUH
[
,05B3
,QWHUUXSW0DS5HJLVWHU 3&,
[
,05B3%
,QWHUUXSW0DS5HJLVWHU 3URFHVVRU%XV
[&
,05B3%
,QWHUUXSW0DS5HJLVWHU 3URFHVVRU%XV
[
,05B0,6&
,QWHUUXSW0DS5HJLVWHU 0LVFHOODQHRXV
[
,'5
,QWHUUXSW'LUHFWLRQ5HJLVWHU
[
±
[& 0%2;
±
0%2;
0DLOER[WR5HJLVWHUV
[
6(0$
6HPDSKRUH5HJLVWHU
[
6(0$
6HPDSKRUH5HJLVWHU