Справочник Пользователя для Interphase Tech 4538
Chapter 1: Hardware Description
4538 Hardware Reference Manual
19
PowerSpan I²O Registers
The PowerSpan includes I²O messaging queues controlled by several registers. These
registers are mapped in two places in the PCI memory space: at the base address defined in
the PCI configuration register 0x10 PCIBAR0 and in the PowerSpan internal register space
(base address defined in PCI configuration register 0x14 PCIBAR1). They are also mapped
in the local space for the local processor (base address 0xF0020000).
registers are mapped in two places in the PCI memory space: at the base address defined in
the PCI configuration register 0x10 PCIBAR0 and in the PowerSpan internal register space
(base address defined in PCI configuration register 0x14 PCIBAR1). They are also mapped
in the local space for the local processor (base address 0xF0020000).
Interrupt Pins and Doorbell Usage
The PowerSpan provides one interrupt pin on the PCI side (–INTA) and six other interrupt
pins (–INT0 to –INT5) on the local side. On the 4538, only –INTA and –INT0 are used for
true interrupt functions. The five other pins are used as I/O pins to control several signals.
pins (–INT0 to –INT5) on the local side. On the 4538, only –INTA and –INT0 are used for
true interrupt functions. The five other pins are used as I/O pins to control several signals.
The PowerSpan offers the ability to map any interrupt source to any interrupt pin. This
capability is used to divert interrupts –INT1 to –INT5 from a pure interrupt function usage.
capability is used to divert interrupts –INT1 to –INT5 from a pure interrupt function usage.
Table 1-20. PowerSpan I²O Registers
Offset
Register
Description
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[
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[
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[
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