Инструкции для Intel III Xeon 733 MHz

Содержание

• Product Features

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• 1. INTRODUCTION

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• 2. TERMINOLOGY

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  • 2.1 S.E.C. CARTRIDGE TERMINOLOGY

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• Additional terms referred to in this and other related documentation:

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  • State of Data

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  • References

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• 3. ELECTRICAL SPECIFICATIONS

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  • System Bus and VREF

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  • Power and Ground Pins

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  • Decoupling Guidelines

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    • 3.3.1 VCC_CORE

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    • LEVEL 2 CACHE DECOUPLING

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    • SYSTEM BUS AGTL+ DECOUPLING

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  • Clock Frequencies and System Bus Clock Ratios

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    • MIXING PROCESSORS OF DIFFERENT FREQUENCIES

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  • Voltage Identification

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  • System Bus Unused Pins and Test Pins

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  • System Bus Signal Groups

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    • ASYNCHRONOUS VS. SYNCHRONOUS FOR SYSTEM BUS SIGNALS

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  • Access Port (TAP) Connection

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  • Maximum Ratings

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  • Processor DC Specifications

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  • AGTL+ System Bus Specifications

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  • System Bus AC Specifications

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          • Table€12. System Bus AC Specifications (Clock) at the processor Core Pins 1, 2, 3

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  • 4

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• 4. Signal Quality

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  • 4.1 Bus Clock Signal Quality Specifications

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  • 4.2 AGTL+ Signal Quality Specifications

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    • 4.2.2 AGTL+ Signal Quality Specifications

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    • 4.2.3 AGTL+ OVERSHOOT/UNDERSHOOT GUIDELINES

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      • 4.2.3.1 Overshoot/Undershoot Magnitude

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      • 4.2.3.2 Overshoot/Undershoot Pulse Duration

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      • 4.2.3.3 Overshoot/Undershoot Activity Factor

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      • 4.2.3.4 Determining if a System Meets the Overshoot/Undershoot Specifications

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• NOTES:

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  • 4.3 Non-GTL+ Signal Quality Specifications

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    • 4.3.1 2.5V Signal Overshoot/Undershoot Guidelines

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• Max Pulse Duration (nS)

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• NOTES:

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    • 4.3.2 BCLK Overshoot/Undershoot Guidelines and Specifications

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    • 4.3.3 Measuring BCLK Overshoot/Undershoot

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    • 4.3.4 2.5V TOLERANT BUFFER RINGBACK SPECIFICATION

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    • 4.3.5 2.5V TOLERANT BUFFER SETTLING LIMIT GUIDELINE

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• 5. PROCESSOR FEATURES

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  • 5.1 Low Power States and Clock Control

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    • NORMAL STATE — STATE 1

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    • AUTO HALT POWER DOWN STATE — STATE 2

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    • STOP-GRANT STATE — STATE 3

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    • HALT/GRANT SNOOP STATE — STATE 4

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    • SLEEP STATE — STATE 5

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    • CLOCK CONTROL

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  • System Management Bus (SMBus) Interface

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    • PROCESSOR INFORMATION ROM

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    • SCRATCH EEPROM

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    • PROCESSOR INFORMATION ROM AND SCRATCH EEPROM SUPPORTED SMBUS TRANSACTIONS

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    • THERMAL SENSOR

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    • THERMAL SENSOR SUPPORTED SMBUS TRANSACTIONS

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    • THERMAL SENSOR REGISTERS

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      • Thermal Reference Registers

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      • Thermal Limit Registers

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      • Status Register

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      • Configuration Register

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      • Conversion Rate Register

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    • SMBus Device Addressing

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• 6. THERMAL SPECIFICATIONS AND DESIGN CONSIDERATIONS

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  • Thermal Specifications

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    • POWER DISSIPATION

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• NOTES:

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    • PLATE FLATNESS SPECIFICATION

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  • Processor Thermal Analysis

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    • THERMAL SOLUTION PERFORMANCE

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    • THERMAL PLATE TO HEAT SINK INTERFACE MANAGEMENT GUIDE

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• NOTES:

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    • MEASUREMENTS FOR THERMAL SPECIFICATIONS

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      • Plate Temperature Measurement

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• 7. MECHANICAL SPECIFICATIONS

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  • 7.1 Weight

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  • 7.2 Cartridge to Connector Mating Details

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  • 7.3 Substrate Edge Finger Signal Listing

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• 8. INTEGRATION TOOLS

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  • 8.1 In-Target Probe (ITP)

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    • 8.1.1 PRIMARY FUNCTION

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    • 8.1.2 DEBUG PORT CONNECTOR DESCRIPTION

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    • 8.1.3 KEEP OUT CONCERNS

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    • 8.1.4 ADDITIONAL INTEGRATION TOOL MECHANICAL KEEP OUTS

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    • 8.1.5 DEBUG PORT SIGNAL DESCRIPTIONS

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    • 8.1.6 DEBUG PORT SIGNAL NOTES

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      • 8.1.6.1 General Signal Quality Notes

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      • 8.1.6.2 Signal Note: DBRESET#

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      • 8.1.6.3 Signal Note: TDO and TDI

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      • 8.1.6.4 Signal Note: TCK and TMS

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    • 8.1.7 Using the TAP to Communicate to the processor

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  • 8.2 Logic Analyzer Interconnect (LAI) and Trace Capture Tool Considerations

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    • 8.2.1 LAI and Trace Capture Tool System Design Considerations

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    • 8.2.2 LAI and Trace Capture tool Mechanical Keep Outs

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• 9. BOXED PROCESSOR SPECIFICATIONS

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  • 9.1 Introduction

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  • 9.2 Mechanical Specifications

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    • 9.2.1 BOXED PROCESSOR HEATSINK DIMENSIONS

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    • 9.2.2 BOXED PROCESSOR HEATSINK WEIGHT

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    • 9.2.3 BOXED PROCESSOR RETENTION MECHANISM

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  • 9.3 Thermal Specifications

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    • 9.3.1 Boxed Processor Cooling Requirements

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    • 9.3.2 Boxed Processor Passive Heatsink Performance

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    • 9.3.2 Optional auxiliary fan attachment

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      • 9.3.2.1 Clearance recommendations for auxiliary fan

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      • 9.3.2.2 Fan power recommendations for auxiliary fan

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      • 9.3.2.3 Thermal evaluation for auxiliary fan

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• 10. APPENDIX

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  • 10.1 Alphabetical Signals Reference

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    • 10.1.1 A[35:03]# (I/O)

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    • 10.1.2 A20M# (I)

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    • 10.1.3 ADS# (I/O)

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    • 10.1.4 AERR# (I/O)

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    • 10.1.5 AP[1:0]# (I/O)

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    • 10.1.6 BCLK (I)

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    • 10.1.7 BERR# (I/O)

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    • 10.1.8 BINIT# (I/O)

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    • 10.1.9 BNR# (I/O)

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    • 10.1.10 BP[3:2]# (I/O)

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    • 10.1.11 BPM[1:0]# (I/O)

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    • 10.1.12 BPRI# (I)

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    • 10.1.13 BR0# (I/O), BR[3:1]# (I)

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    • 10.1.15 CORE_AN_SENSE (O)

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    • 10.1.16 D[63:00]# (I/O)

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    • 10.1.17 DBSY# (I/O)

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    • 10.1.18 DEFER# (I)

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    • 10.1.19 DEP[7:0]# (I/O)

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    • 10.1.20 DRDY# (I/O)

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    • 10.1.21 FERR# (O)

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    • 10.1.22 FLUSH# (I)

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    • 10.1.23 HIT# (I/O), HITM# (I/O)

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    • 10.1.24 HV_EN# (O)

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    • 10.1.25 IERR# (O)

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    • 10.1.26 IGNNE# (I)

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    • 10.1.27 INIT# (I)

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    • 10.1.28 INTR - see LINT[0]

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    • 10.1.29 LINT[1:0] (I)

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    • 10.1.30 LOCK# (I/O)

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    • 10.1.31 L2_SENSE

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    • 10.1.32 OCVR_EN (I)

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    • 10.1.33 OCVR_OK(O)

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    • 10.1.34 NMI - See LINT[1]

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    • 10.1.35 PICCLK (I)

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    • 10.1.36 PICD[1:0] (I/O)

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    • 10.1.37 PRDY# (O)

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    • 10.1.38 PREQ# (I)

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    • 10.1.39 PWREN[1:0] (I)

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    • 10.1.40 PWRGOOD (I)

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              • Figure€41. PWRGD Relationship at Power-On

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    • 10.1.41 REQ[4:0]# (I/O)

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    • 10.1.42 RESET# (I)

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    • 10.1.43 RP# (I/O)

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    • 10.1.44 RS[2:0]# (I)

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    • 10.1.45 RSP# (I)

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    • 10.1.46 SA[2:0] (I)

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    • 10.1.47 SELFSB0 (I) SELFSB1 (O)

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    • 10.1.48 SLP# (I)

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    • 10.1.49 SMBALERT# (O)

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    • 10.1.50 SMBCLK (I)

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    • 10.1.51 SMBDAT (I/O)

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    • 10.1.52 SMI# (I)

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    • 10.1.53 STPCLK# (I)

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    • 10.1.54 TCK (I)

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    • 10.1.55 TDI (I)

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    • 10.1.56 TDO (O)

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    • 10.1.57 TEST_2.5_[A23, A62, B27] (I)

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    • 10.1.58 THERMTRIP# (O)

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    • 10.1.59 TMS (I)

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    • 10.1.60 TRDY# (I)

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    • 10.1.61 TRST# (I)

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    • 10.1.62 VID_L2[4:0], VID_CORE[4:0] (O)

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    • 10.1.63 VIN_SENSE

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    • 10.1.64 WP (I)

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  • 10.2 Signal Summaries

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