Texas Instruments TMS320DM646x 用户手册

lists the memory-mapped registers for the EMAC. See the device-specific data manual for the

memory address of these registers.

0h

TXIDVER

Transmit Identification and Version Register

4h

TXCONTROL

Transmit Control Register

8h

TXTEARDOWN

Transmit Teardown Register

10h

RXIDVER

Receive Identification and Version Register

14h

RXCONTROL

Receive Control Register

18h

RXTEARDOWN

Receive Teardown Register

80h

TXINTSTATRAW

Transmit Interrupt Status (Unmasked) Register

84h

TXINTSTATMASKED

Transmit Interrupt Status (Masked) Register

88h

TXINTMASKSET

Transmit Interrupt Mask Set Register

8Ch

TXINTMASKCLEAR

Transmit Interrupt Clear Register

90h

MACINVECTOR

MAC Input Vector Register

94h

MACEOIVECTOR

MAC End of Interrupt Vector Register

A0h

RXINTSTATRAW

Receive Interrupt Status (Unmasked) Register

A4h

RXINTSTATMASKED

Receive Interrupt Status (Masked) Register

A8h

RXINTMASKSET

Receive Interrupt Mask Set Register

ACh

RXINTMASKCLEAR

Receive Interrupt Mask Clear Register

B0h

MACINTSTATRAW

MAC Interrupt Status (Unmasked) Register

B4h

MACINTSTATMASKED

MAC Interrupt Status (Masked) Register

B8h

MACINTMASKSET

MAC Interrupt Mask Set Register

BCh

MACINTMASKCLEAR

MAC Interrupt Mask Clear Register

100h

RXMBPENABLE

Receive Multicast/Broadcast/Promiscuous Channel Enable Register

104h

RXUNICASTSET

Receive Unicast Enable Set Register

108h

RXUNICASTCLEAR

Receive Unicast Clear Register

10Ch

RXMAXLEN

Receive Maximum Length Register

110h

RXBUFFEROFFSET

Receive Buffer Offset Register

114h

RXFILTERLOWTHRESH

Receive Filter Low Priority Frame Threshold Register

120h

RX0FLOWTHRESH

Receive Channel 0 Flow Control Threshold Register

124h

RX1FLOWTHRESH

Receive Channel 1 Flow Control Threshold Register

128h

RX2FLOWTHRESH

Receive Channel 2 Flow Control Threshold Register

12Ch

RX3FLOWTHRESH

Receive Channel 3 Flow Control Threshold Register

130h

RX4FLOWTHRESH

Receive Channel 4 Flow Control Threshold Register

134h

RX5FLOWTHRESH

Receive Channel 5 Flow Control Threshold Register

138h

RX6FLOWTHRESH

Receive Channel 6 Flow Control Threshold Register

13Ch

RX7FLOWTHRESH

Receive Channel 7 Flow Control Threshold Register

140h

RX0FREEBUFFER

Receive Channel 0 Free Buffer Count Register

144h

RX1FREEBUFFER

Receive Channel 1 Free Buffer Count Register

148h

RX2FREEBUFFER

Receive Channel 2 Free Buffer Count Register

14Ch

RX3FREEBUFFER

Receive Channel 3 Free Buffer Count Register

150h

RX4FREEBUFFER

Receive Channel 4 Free Buffer Count Register

154h

RX5FREEBUFFER

Receive Channel 5 Free Buffer Count Register

158h

RX6FREEBUFFER

Receive Channel 6 Free Buffer Count Register

15Ch

RX7FREEBUFFER

Receive Channel 7 Free Buffer Count Register

160h

MACCONTROL

MAC Control Register

84

SPRUEQ6 – December 2007