Nxp Semiconductors UM10237 用户手册

UM10237_2

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Transmit flow control is activated by writing 1 to the TxFlowControl bit of the Command 
register. When the Ethernet block operates in full duplex mode, this will result in 
transmission of IEEE 802.3/31 pause frames. The flow control continues until a 0 is 
written to TxFlowControl bit of the Command register.

If the MAC is operating in full-duplex mode, then setting the TxFlowControl bit of the 
Command register will start a pause frame transmission. The value inserted into the 
pause-timer value field of transmitted pause frames is programmed via the 
PauseTimer[15:0] bits in the FlowControlCounter register. When the TxFlowControl bit is 
deasserted, another pause frame having a pause-timer value of 0x0000 is automatically 
sent to abort flow control and resume transmission.

When flow control be in force for an extended time, a sequence of pause frames must be 
transmitted. This is supported with a mirror counter mechanism. To enable mirror 
counting, a nonzero value is written to the MirrorCounter[15:0] bits in the 
FlowControlCounter register. When the TxFlowControl bit is asserted, a pause frame is 
transmitted. After sending the pause frame, an internal mirror counter is initialized to zero. 
The internal mirror counter starts incrementing one every 512 bit-slot times. When the 
internal mirror counter reaches the MirrorCounter value, another pause frame is 
transmitted with pause-timer value equal to the PauseTimer field from the 
FlowControlCounter register, the internal mirror counter is reset to zero and restarts 
counting. The register MirrorCounter[15:0] is usually set to a smaller value than register 
PauseTimer[15:0] to ensure an early expiration of the mirror counter, allowing time to send 
a new pause frame before the transmission on the other side can resume. By continuing 
to send pause frames before the transmitting side finishes counting the pause timer, the 
pause can be extended as long as TxFlowControl is asserted. This continues until 
TxFlowControl is deasserted when a final pause frame having a pause-timer value of 
0x0000 is automatically sent to abort flow control and resume transmission. To disable the 
mirror counter mechanism, write the value 0 to MirrorCounter field in the 
FlowControlCounter register. When using the mirror counter mechanism, account for 
time-of-flight delays, frame transmission time, queuing delays, crystal frequency 
tolerances, and response time delays by programming the MirrorCounter conservatively, 
typically about 80% of the PauseTimer value.

If the software device driver sets the MirrorCounter field of the FlowControlCounter 
register to zero, the Ethernet block will only send one pause control frame. After sending 
the pause frame an internal pause counter is initialized at zero; the internal pause counter 
is incremented by one every 512 bit-slot times. Once the internal pause counter reaches 
the value of the PauseTimer register, the TxFlowControl bit in the Command register will 
be reset. The software device driver can poll the TxFlowControl bit to detect when the 
pause completes.

The value of the internal counter in the flow control module can be read out via the 
FlowControlStatus register. If the MirrorCounter is nonzero, the FlowControlStatus register 
will return the value of the internal mirror counter; if the MirrorCounter is zero the 
FlowControlStatus register will return the value of the internal pause counter value.

The device driver is allowed to dynamically modify the MirrorCounter register value and 
switch between zero MirrorCounter and nonzero MirrorCounter modes.