Nxp Semiconductors UM10237 用户手册

UM10237_2

© NXP B.V. 2008. All rights reserved.

The SPI contains 5 registers as shown in 

. All registers are byte, half word 

and word accessible.

 

[1]

Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

The S0SPCR register controls the operation of the SPI0 as per the configuration bits 
setting.

 

S0SPCR

SPI Control Register. This register controls the 
operation of the SPI.

R/W

0x00

0xE002 0000

S0SPSR

SPI Status Register. This register shows the 
status of the SPI.

RO

0x00

0xE002 0004

S0SPDR

SPI Data Register. This bi-directional register 
provides the transmit and receive data for the 
SPI. Transmit data is provided to the SPI0 by 
writing to this register. Data received by the SPI0 
can be read from this register.

R/W

0x00

0xE002 0008

S0SPCCR SPI Clock Counter Register. This register 

controls the frequency of a master’s SCK0.

R/W

0x00

0xE002 000C

S0SPINT

SPI Interrupt Flag. This register contains the 
interrupt flag for the SPI interface.

R/W

0x00

0xE002 001C

1:0

-

Reserved, user software should not write ones to 
reserved bits. The value read from a reserved bit is not 
defined.

NA

2

BitEnable

0

The SPI controller sends and receives 8 bits of data per 
transfer.

0

1

The SPI controller sends and receives the number of bits 
selected by bits 11:8.

3

CPHA

0

Clock phase control determines the relationship between 
the data and the clock on SPI transfers, and controls 
when a slave transfer is defined as starting and ending.

Data is sampled on the first clock edge of SCK. A transfer 
starts and ends with activation and deactivation of the 
SSEL signal.

0

1

Data is sampled on the second clock edge of the SCK. A 
transfer starts with the first clock edge, and ends with the 
last sampling edge when the SSEL signal is active.

4

CPOL

0

Clock polarity control.

SCK is active high.

0

1

SCK is active low.