Nxp Semiconductors UM10237 用户手册

UM10237_2

© NXP B.V. 2008. All rights reserved.

The S0SPSR register controls the operation of the SPI0 as per the configuration bits 
setting.

 

5

MSTR

0

Master mode select.

The SPI operates in Slave mode.

0

1

The SPI operates in Master mode.

6

LSBF

0

LSB First controls which direction each byte is shifted 
when transferred.

SPI data is transferred MSB (bit 7) first.

0

1

SPI data is transferred LSB (bit 0) first.

7

SPIE

0

Serial peripheral interrupt enable.

SPI interrupts are inhibited.

0

1

A hardware interrupt is generated each time the SPIF or 
MODF bits are activated.

11:8

BITS

When bit 2 of this register is 1, this field controls the 
number of bits per transfer:

0000

1000

8 bits per transfer

1001

9 bits per transfer

1010

10 bits per transfer

1011

11 bits per transfer

1100

12 bits per transfer

1101

13 bits per transfer

1110

14 bits per transfer

1111

15 bits per transfer

0000

16 bits per transfer

15:12

-

Reserved, user software should not write ones to 
reserved bits. The value read from a reserved bit is not 
defined.

NA

2:0

-

Reserved, user software should not write ones to reserved bits. 
The value read from a reserved bit is not defined.

NA

3

ABRT

Slave abort. When 1, this bit indicates that a slave abort has 
occurred. This bit is cleared by reading this register.

0

4

MODF

Mode fault. when 1, this bit indicates that a Mode fault error has 
occurred. This bit is cleared by reading this register, then writing 
the SPI0 control register. 

0