Nxp Semiconductors UM10237 用户手册
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
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NXP Semiconductors
UM10237
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
6.1.13 Configuration Register (DMACConfiguration - 0xFFE0 4030)
The DMACConfiguration Register is read/write and configures the operation of the
GPDMA. The endianness of the AHB master interface can be altered by writing to the M
bit of this register. The AHB master interface is set to little-endian mode on reset.
GPDMA. The endianness of the AHB master interface can be altered by writing to the M
bit of this register. The AHB master interface is set to little-endian mode on reset.
6.1.14 Synchronization Register (DMACSync - 0xFFE0 4034)
The DMACSync Register is read/write and enables or disables synchronization logic for
the DMA request signals. The DMA request signals consist of the DMACBREQ[15:0],
DMACSREQ[15:0], DMACLBREQ[15:0], and DMACLSREQ[15:0]. A bit set to 0 enables
the synchronization logic for a particular group of DMA requests. A bit set to 1 disables the
synchronization logic for a particular group of DMA requests. This register is reset to 0,
synchronization logic enabled.
the DMA request signals. The DMA request signals consist of the DMACBREQ[15:0],
DMACSREQ[15:0], DMACLBREQ[15:0], and DMACLSREQ[15:0]. A bit set to 0 enables
the synchronization logic for a particular group of DMA requests. A bit set to 1 disables the
synchronization logic for a particular group of DMA requests. This register is reset to 0,
synchronization logic enabled.
Table 665. Software Last Single Request register (DMACSoftLSReq - address 0xFFE0 402C)
bit description
Bit
Symbol
Description
Reset
Value
Value
3:0
-
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
bits. The value read from a reserved bit is not defined.
NA
4
SoftLSReqSDMMC
Software last single request flags for SD/MMC.
0
31:5
-
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
bits. The value read from a reserved bit is not defined.
NA
Table 666. Configuration register (DMACConfiguration - address 0xFFE0 4030) bit
description
Bit
Symbol Value
Description
Reset
Value
Value
0
E
GPDMA enable:
0
0
Disabled. Disabling the GPDMA reduces power consumption.
1
Enabled.
1
M
AHB Master endianness configuration:
0
0
Little-endian mode.
1
Big-endian mode.
31:2
-
-
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
The value read from a reserved bit is not defined.
NA
Table 667. Synchronization register (DMACSync - address 0xFFE0 4034) bit description
Bit
Symbol
Description
Reset
Value
Value
15:0
DMACSync
DMA synchronization logic for DMA request signals enabled or
disabled. A LOW bit indicates that the synchronization logic for
the DMACBREQ[15:0], DMACSREQ[15:0],
DMACLBREQ[15:0], and DMACLSREQ[15:0] request signals
is enabled. A HIGH bit indicates that the synchronization logic
is disabled.
disabled. A LOW bit indicates that the synchronization logic for
the DMACBREQ[15:0], DMACSREQ[15:0],
DMACLBREQ[15:0], and DMACLSREQ[15:0] request signals
is enabled. A HIGH bit indicates that the synchronization logic
is disabled.
0x0000
31:16 -
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
The value read from a reserved bit is not defined.
NA