Nxp Semiconductors UM10237 用户手册
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
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NXP Semiconductors
UM10237
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
6.2 Channel registers
The channel registers are used to program the two DMA channels. These registers
consist of:
consist of:
•
Two DMACCxSrcAddr Registers
•
Two DMACCxDestAddr Registers
•
Two DMACCxLLI Registers
•
Two DMACCxControl Registers
•
Two DMACCxConfiguration Registers
When performing scatter/gather DMA the first four registers are automatically updated.
6.2.1 Channel Source Address Registers (DMACC0SrcAddr - 0xFFE0 4100 and
DMACC1SrcAddr - 0xFFE0 4120)
The two read/write DMACCxSrcAddr Registers contain the current source address
(byte-aligned) of the data to be transferred. Each register is programmed directly by
software before the appropriate channel is enabled. When the DMA channel is enabled
this register is updated:
(byte-aligned) of the data to be transferred. Each register is programmed directly by
software before the appropriate channel is enabled. When the DMA channel is enabled
this register is updated:
•
As the source address is incremented.
•
By following the linked list when a complete packet of data has been transferred.
Reading the register when the channel is active does not provide useful information. This
is because by the time software has processed the value read, the channel might have
progressed. It is intended to be read only when the channel has stopped, in which case it
shows the source address of the last item read.
is because by the time software has processed the value read, the channel might have
progressed. It is intended to be read only when the channel has stopped, in which case it
shows the source address of the last item read.
Note: The source and destination addresses must be aligned to the source and
destination widths.
destination widths.
6.2.2 Channel Destination Address Registers (DMACC0DestAddr - 0xFFE0 4104
and DMACC1DestAddr - 0xFFE0 4124)
The two read/write DMACCxDestAddr Registers contain the current destination address
(byte-aligned) of the data to be transferred. Each register is programmed directly by
software before the channel is enabled. When the DMA channel is enabled the register is
updated as the destination address is incremented and by following the linked list when a
complete packet of data has been transferred. Reading the register when the channel is
active does not provide useful information. This is because by the time that software has
processed the value read, the channel might have progressed. It is intended to be read
only when a channel has stopped, in which case it shows the destination address of the
last item read.
(byte-aligned) of the data to be transferred. Each register is programmed directly by
software before the channel is enabled. When the DMA channel is enabled the register is
updated as the destination address is incremented and by following the linked list when a
complete packet of data has been transferred. Reading the register when the channel is
active does not provide useful information. This is because by the time that software has
processed the value read, the channel might have progressed. It is intended to be read
only when a channel has stopped, in which case it shows the destination address of the
last item read.
shows the bit assignments of the DMACCxDestAddr
Register.
Table 668. Channel Source Address registers (DMACC0SrcAddr - address 0xFFE0 4100 and
DMACC1SrcAddr - address 0xFFE0 4120) bit description
Bit
Symbol
Description
Reset Value
31:0
SrcAddr
DMA source address.
0x0000 0000