Nxp Semiconductors UM10237 用户手册
UM10237_2
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User manual
Rev. 02 — 19 December 2008
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NXP Semiconductors
UM10237
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
6.2.3 Channel Linked List Item Registers (DMACC0LLI - 0xFFE0 4108 and
DMACC1LLI - 0xFFE0 4128)
The two read/write DMACCxLLI Registers contain a word-aligned address of the next
Linked List Item (LLI). If the LLI is 0, then the current LLI is the last in the chain, and the
DMA channel is disabled when all DMA transfers associated with it are completed.
Linked List Item (LLI). If the LLI is 0, then the current LLI is the last in the chain, and the
DMA channel is disabled when all DMA transfers associated with it are completed.
Note: Programming this register when the DMA channel is enabled has unpredictable
side effects.
side effects.
Note: To make loading the LLIs more efficient for some systems, the LLI data structures
can be made four-word aligned.
can be made four-word aligned.
6.2.4 Channel Control Registers (DMACC0Control - 0xFFE0 410C and
DMACC0Control - 0xFFE0 412C)
The two read/write DMACCxControl Registers contain DMA channel control information
such as the transfer size, burst size, and transfer width. Each register is programmed
directly by software before the DMA channel is enabled. When the channel is enabled the
register is updated by following the linked list when a complete packet of data has been
transferred. Reading the register while the channel is active does not give useful
information. This is because by the time software has processed the value read, the
channel might have progressed. It is intended to be read only when a channel has
stopped.
such as the transfer size, burst size, and transfer width. Each register is programmed
directly by software before the DMA channel is enabled. When the channel is enabled the
register is updated by following the linked list when a complete packet of data has been
transferred. Reading the register while the channel is active does not give useful
information. This is because by the time software has processed the value read, the
channel might have progressed. It is intended to be read only when a channel has
stopped.
Table 669. Channel Destination Address registers (DMACC0DestAddr - address
0xFFE0 4104 and DMACC1DestAddr - address 0xFFE0 4124) bit description
Bit
Symbol
Description
Reset Value
31:0
DestAddr
DMA destination address
0x0000 0000
Table 670. Channel Linked List Item registers (DMACC0LLI - address 0xFFE0 4108 and
DMACC1LLI - address 0xFFE0 4128) bit description
Bit
Symbol
Description
Reset Value
0
Reserved Reserved, read as zero, do not modify.
NA
1
R
Reserved, and must be written as 0, masked on read.
0
31:2
LLI
Linked list item. Bits [31:2] of the address for the next LLI.
Address bits [1:0] are 0.
Address bits [1:0] are 0.
0