Renesas SH7781 用户手册
20. Graphics Data Translation Accelerator (GDTA)
Rev.1.00 Jan. 10, 2008 Page 981 of 1658
REJ09B0261-0100
20.3.3
GA Interrupt Source Indicating Register (GACISR)
GACISR is in the GDTA common register block and indicates the states of interrupt sources for
each module.
each module.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
30
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
BIt:
Initial value:
R/W:
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CL_END
MC_END
CL_ERR
MC_ERR
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
R
R
R
R
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
BIt:
Initial value:
R/W:
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
31 to 4
⎯ All
0
⎯ Reserved
These bits are always read as 0. The write value should
always be 0.
always be 0.
3
MC_EER
0
R
Indicates whether an MC module error interrupt has
occurred.
occurred.
0: No error
1: Error occurred
2
CL_EER
0
R
Indicates whether a CL module error interrupt has
occurred.
occurred.
0: No error
1: Error occurred
1
MC_END
0
R
Indicates whether an MC module processing end
interrupt has occurred.
interrupt has occurred.
0: '1' has been written to the MC_ENCR bit in GACICR.
1: Processing completed
0
CL_END
0
R
Indicates whether a CL module processing end interrupt
has occurred.
has occurred.
0: '1' has been written to the CL_ENCR bit in GACICR.
1: Processing completed
Note: MC processing completion is indicated when the command processing is complete and the
end command is written to the MC command FIFO (see section 20.3.17, CL Input Y
Padding Size Setting Register (CLIYPR)).
Padding Size Setting Register (CLIYPR)).